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Prof. Stelios Neophytou
University of Nicosia, Cyprus

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Research Keywords & Expertise

0 Connected Devices
0 Emergency evacuation and management
0 ATPG
0 ATPG compaction
0 Autonomous & Connected Vehicles

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Short Biography

Dr Stelios Neophytou is an Associate Professor at the Department of Engineering, University of Nicosia. He received the Engineering Diploma from the Computer Engineering and Informatics Department of University of Patras, Patras, Greece, and the PhD degree from the Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus, in 2003 and 2009, respectively. His research interests fall under Electronic Design Automation focusing on algorithm development for integrated circuits’ design verification and post-manufacturing testing. Specifically, his work involves methodologies for quality enhancement of the Automatic Test Pattern Generation (ATPG) process related to detection of non-modelled defects, test size compaction and scaling in multiprocessing environments. He has also work related to test generation techniques for Built-In Self-Test architectures as well as graph-theoretic problems considering Binary Decision Diagrams.

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Journal article
Published: 23 April 2021 in Sustainability
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The introduction of shared autonomous vehicles into the transport system is suggested to bring significant impacts on traffic conditions, road safety and emissions, as well as overall reshaping travel behaviour. Compared with a private autonomous vehicle, a shared automated vehicle (SAV) is associated with different willingness-to-adopt and willingness-to-pay characteristics. An important aspect of future SAV adoption is the presence of other passengers in the SAV—often people unknown to the cotravellers. This study presents a cross-country exploration of user preferences and WTP calculations regarding mode choice between a private non-autonomous vehicle, and private and shared autonomous vehicles. To explore user preferences, the study launched a survey in seven European countries, including a stated-preference experiment of user choices. To model and quantify the effect of travel mode attributes and socio-demographic characteristics, the study employs a mixed logit model. The model results were the basis for calculating willingness-to-pay values for all countries and travel modes, and provide insight into the significant heterogeneous, gender-wise effect of cotravellers in the choice to use an SAV. The study results highlight the importance of analysis of the effect of SAV attributes and shared-ride conditions on the future acceptance and adoption rates of such services.

ACS Style

Amalia Polydoropoulou; Ioannis Tsouros; Nikolas Thomopoulos; Cristina Pronello; Arnór Elvarsson; Haraldur Sigþórsson; Nima Dadashzadeh; Kristina Stojmenova; Jaka Sodnik; Stelios Neophytou; Domokos Esztergár-Kiss; Jamil Hamadneh; Graham Parkhurst; Shelly Etzioni; Yoram Shiftan; Floridea Di Ciommo. Who Is Willing to Share Their AV? Insights about Gender Differences among Seven Countries. Sustainability 2021, 13, 4769 .

AMA Style

Amalia Polydoropoulou, Ioannis Tsouros, Nikolas Thomopoulos, Cristina Pronello, Arnór Elvarsson, Haraldur Sigþórsson, Nima Dadashzadeh, Kristina Stojmenova, Jaka Sodnik, Stelios Neophytou, Domokos Esztergár-Kiss, Jamil Hamadneh, Graham Parkhurst, Shelly Etzioni, Yoram Shiftan, Floridea Di Ciommo. Who Is Willing to Share Their AV? Insights about Gender Differences among Seven Countries. Sustainability. 2021; 13 (9):4769.

Chicago/Turabian Style

Amalia Polydoropoulou; Ioannis Tsouros; Nikolas Thomopoulos; Cristina Pronello; Arnór Elvarsson; Haraldur Sigþórsson; Nima Dadashzadeh; Kristina Stojmenova; Jaka Sodnik; Stelios Neophytou; Domokos Esztergár-Kiss; Jamil Hamadneh; Graham Parkhurst; Shelly Etzioni; Yoram Shiftan; Floridea Di Ciommo. 2021. "Who Is Willing to Share Their AV? Insights about Gender Differences among Seven Countries." Sustainability 13, no. 9: 4769.

Journal article
Published: 23 November 2020 in Sustainability
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The technology that allows fully automated driving already exists and it may gradually enter the market over the forthcoming decades. Technology assimilation and automated vehicle acceptance in different countries is of high interest to many scholars, manufacturers, and policymakers worldwide. We model the mode choice between automated vehicles and conventional cars using a mixed multinomial logit heteroskedastic error component type model. Specifically, we capture preference heterogeneity assuming a continuous distribution across individuals. Different choice scenarios, based on respondents’ reported trip, were presented to respondents from six European countries: Cyprus, Hungary, Iceland, Montenegro, Slovenia, and the UK. We found that large reservations towards automated vehicles exist in all countries with 70% conventional private car choices, and 30% automated vehicles choices. We found that men, under the age of 60, with a high income who currently use private car, are more likely to be early adopters of automated vehicles. We found significant differences in automated vehicles acceptance in different countries. Individuals from Slovenia and Cyprus show higher automated vehicles acceptance while individuals from wealthier countries, UK, and Iceland, show more reservations towards them. Nontrading mode choice behaviors, value of travel time, and differences in model parameters among the different countries are discussed.

ACS Style

Shelly Etzioni; Jamil Hamadneh; Arnór Elvarsson; Domokos Esztergár-Kiss; Milena Djukanovic; Stelios Neophytou; Jaka Sodnik; Amalia Polydoropoulou; Ioannis Tsouros; Cristina Pronello; Nikolas Thomopoulos; Yoram Shiftan. Modeling Cross-National Differences in Automated Vehicle Acceptance. Sustainability 2020, 12, 9765 .

AMA Style

Shelly Etzioni, Jamil Hamadneh, Arnór Elvarsson, Domokos Esztergár-Kiss, Milena Djukanovic, Stelios Neophytou, Jaka Sodnik, Amalia Polydoropoulou, Ioannis Tsouros, Cristina Pronello, Nikolas Thomopoulos, Yoram Shiftan. Modeling Cross-National Differences in Automated Vehicle Acceptance. Sustainability. 2020; 12 (22):9765.

Chicago/Turabian Style

Shelly Etzioni; Jamil Hamadneh; Arnór Elvarsson; Domokos Esztergár-Kiss; Milena Djukanovic; Stelios Neophytou; Jaka Sodnik; Amalia Polydoropoulou; Ioannis Tsouros; Cristina Pronello; Nikolas Thomopoulos; Yoram Shiftan. 2020. "Modeling Cross-National Differences in Automated Vehicle Acceptance." Sustainability 12, no. 22: 9765.

Journal article
Published: 29 October 2019 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ACS Style

Stavros Hadjitheophanous; Stelios N. Neophytou; Maria K. Michael. Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2019, 28, 553 -564.

AMA Style

Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael. Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2019; 28 (2):553-564.

Chicago/Turabian Style

Stavros Hadjitheophanous; Stelios N. Neophytou; Maria K. Michael. 2019. "Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 2: 553-564.

Article
Published: 15 November 2018 in Journal of Electronic Testing
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The efficient representation and manipulation of a large number of paths in a Directed Acyclic Graph (DAG) requires the usage of special data structures that may become of exponential size with respect to the size of the graph. Several methodologies targeting Electronic Design Automation problems such as timing analysis, physical design, verification and testing involve path representation and necessary manipulation. Previous works proposed an encoding using Zero-suppressed Binary Decision Diagrams (ZDDs), which has been shown experimentally to cope well when representing structural or logical paths in VLSI circuits. However, it is well known that the ordering of the variables in a ZDD highly affects its size and, therefore, the efficiency of the methodologies utilizing these data structures. In this work, we show that using a reverse topological order for the ZDD variables bounds the number of nodes in the ZDD representing structural paths to the number of edges in the DAG considered, hence, making the ZDD size linear to the DAG’s size. This result, supported here both theoretically and experimentally, is very important as it can render methodologies with questionable scalability applicable to larger industrial designs. We demonstrate the applicability of the proposed variable ordering in one such methodology which utilizes ZDDs to grade the Path Delay Fault coverage of a given test set.

ACS Style

Stelios N. Neophytou; Maria K. Michael. Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering. Journal of Electronic Testing 2018, 34, 667 -683.

AMA Style

Stelios N. Neophytou, Maria K. Michael. Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering. Journal of Electronic Testing. 2018; 34 (6):667-683.

Chicago/Turabian Style

Stelios N. Neophytou; Maria K. Michael. 2018. "Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering." Journal of Electronic Testing 34, no. 6: 667-683.

Journal article
Published: 12 July 2018 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Current and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This work proposes a new parallel methodology targeting the fault simulation problem, for shared memory multi-core systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid unecessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up.

ACS Style

Stavros Hadjitheophanous; Stelios N. Neophytou; Maria K. Michael. Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2018, 38, 1466 -1479.

AMA Style

Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael. Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018; 38 (8):1466-1479.

Chicago/Turabian Style

Stavros Hadjitheophanous; Stelios N. Neophytou; Maria K. Michael. 2018. "Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 8: 1466-1479.

Chapter
Published: 30 August 2017 in Dependable Multicore Architectures at Nanoscale
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This chapter discusses dependability threads for modern integrated circuits that affect both their correct operation and performance. The text provides an overview of fault/error models adopted in methodologies for dependability assessment, analysis, and mitigation. Faults are categorized based on their applicability in the various abstraction layers. Their applicability to modern design trends such as FPGAs and NoCs is also presented. Furthermore, models for emerging and future dependability issues are discussed in the same rationale. In particular, special attention is given to those issues that typically arise during the operational life of the devices, causing either transient, intermittent or permanent failures, including aging and wear-out effects that directly affect their lifetime.

ACS Style

Cristiana Bolchini; Maria K. Michael; Antonio Miele; Stelios Neophytou. Dependability Threats. Dependable Multicore Architectures at Nanoscale 2017, 37 -92.

AMA Style

Cristiana Bolchini, Maria K. Michael, Antonio Miele, Stelios Neophytou. Dependability Threats. Dependable Multicore Architectures at Nanoscale. 2017; ():37-92.

Chicago/Turabian Style

Cristiana Bolchini; Maria K. Michael; Antonio Miele; Stelios Neophytou. 2017. "Dependability Threats." Dependable Multicore Architectures at Nanoscale , no. : 37-92.

Conference paper
Published: 01 May 2016 in 2016 21th IEEE European Test Symposium (ETS)
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A new test generation methodology is proposed that takes advantage of shared memory multi-core systems. Appropriate parallelization of the main steps of ATPG allocates resources in order to minimize workload duplication and multi-threading race contention, often encountered in parallel implementations. The proposed approach ensures that the obtained acceleration grows linearly with the number of processing cores and, at the same time, keeps the test set size close to that obtained by serial ATPG. The experimental results demonstrate that the proposed methodology achieves higher degree of speed-up than comparable state-of-the-art multi-core based tools, while maintains similar test set sizes.

ACS Style

Stavros Hadjitheophanous; Stelios N. Neophytou; Maria K. Michael. Utilizing shared memory multi-cores to speed-up the ATPG process. 2016 21th IEEE European Test Symposium (ETS) 2016, 1 -6.

AMA Style

Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael. Utilizing shared memory multi-cores to speed-up the ATPG process. 2016 21th IEEE European Test Symposium (ETS). 2016; ():1-6.

Chicago/Turabian Style

Stavros Hadjitheophanous; Stelios N. Neophytou; Maria K. Michael. 2016. "Utilizing shared memory multi-cores to speed-up the ATPG process." 2016 21th IEEE European Test Symposium (ETS) , no. : 1-6.

Proceedings article
Published: 01 April 2016 in 2016 IEEE 34th VLSI Test Symposium (VTS)
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Multicore architectures can significantly accelerate the performance of well-established design and test automation processes, provided that the underlying process is scalable with respect to the system on which it is executed. In this work we concentrate on fault simulation and propose a new parallel process for shared-memory multicore systems, capable of maintaining its scalability as the number of processing cores utilized increases. In order to maximize parallelization, the method utilizes a simple, non-optimized single thread simulation process, which allows for high degrees of freedom to be exploited by three different and combined dimensions of parallelism. Simulation data is distributed to the available cores in a balanced fashion in order to favor speed-up over single-core executions and, ultimately, scalability. The experimental results show that the proposed approach achieves high speed-up rates which, in contrast to comparable state-of the-art methods, increase monotonically with the number of cores demonstrating a highly scalable solution.

ACS Style

Stavros Hadjitheophanous; Stelios N. Neophytou; Maria K. Michael. Scalable parallel fault simulation for shared-memory multiprocessor systems. 2016 IEEE 34th VLSI Test Symposium (VTS) 2016, 1 -6.

AMA Style

Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael. Scalable parallel fault simulation for shared-memory multiprocessor systems. 2016 IEEE 34th VLSI Test Symposium (VTS). 2016; ():1-6.

Chicago/Turabian Style

Stavros Hadjitheophanous; Stelios N. Neophytou; Maria K. Michael. 2016. "Scalable parallel fault simulation for shared-memory multiprocessor systems." 2016 IEEE 34th VLSI Test Symposium (VTS) , no. : 1-6.

Conference paper
Published: 25 March 2016 in Transactions on Petri Nets and Other Models of Concurrency XV
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Sensor networks for the assessment of physical threats in critical infrastructure have the potential to provide continuous and reliable information on illegal activity over wide areas. In order to reach that potential, it is essential for the sensor network to operate efficiently by conducting processing and communication operations on a very limited power budget. In this work, it is shown that when sequentially assessing physical threats using a sensor network, the required processing and communication load is directly related to estimation uncertainty. It is, furthermore, shown that the processing and communications rate required for sequential estimation using a sensor network is much less than the rate required for processing and transmitting all data available at the nodes. This result can be used to reduce hardware cost and power requirements of the sensor network.

ACS Style

Ioannis Kyriakides; Stelios Neophytou; Anastasis Kounoudes; Konstantinos Michail; Yiannis Argyrou; Thomas Wieland. Processing and Communications Rate Requirements in Sensor Networks for Physical Thread Assessment. Transactions on Petri Nets and Other Models of Concurrency XV 2016, 31 -36.

AMA Style

Ioannis Kyriakides, Stelios Neophytou, Anastasis Kounoudes, Konstantinos Michail, Yiannis Argyrou, Thomas Wieland. Processing and Communications Rate Requirements in Sensor Networks for Physical Thread Assessment. Transactions on Petri Nets and Other Models of Concurrency XV. 2016; ():31-36.

Chicago/Turabian Style

Ioannis Kyriakides; Stelios Neophytou; Anastasis Kounoudes; Konstantinos Michail; Yiannis Argyrou; Thomas Wieland. 2016. "Processing and Communications Rate Requirements in Sensor Networks for Physical Thread Assessment." Transactions on Petri Nets and Other Models of Concurrency XV , no. : 31-36.

Proceedings article
Published: 01 May 2015 in 2015 20th IEEE European Test Symposium (ETS)
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The high accuracy of the Path Delay Fault model (PDF) is usually sidelined by its high complexity since the number of possible faults can become exponential to the circuit size (even when only critical faults are considered). Thus, fault simulation may require prohibitively large memory resources. In this work we propose a test reordering technique to control the complexity of exact PDF grading when Zero-suppressed Binary Decision Diagrams are used for fault representation. Experimentation on path dense benchmark circuits demonstrates considerable reduction in memory requirements for the PDF grading problem.

ACS Style

Stelios N. Neophytou; Maria K. Michael; Neophytou S.N.; Michael M.K.. Tackling the complexity of exact path delay fault grading for path intensive circuits. 2015 20th IEEE European Test Symposium (ETS) 2015, 1 -2.

AMA Style

Stelios N. Neophytou, Maria K. Michael, Neophytou S.N., Michael M.K.. Tackling the complexity of exact path delay fault grading for path intensive circuits. 2015 20th IEEE European Test Symposium (ETS). 2015; ():1-2.

Chicago/Turabian Style

Stelios N. Neophytou; Maria K. Michael; Neophytou S.N.; Michael M.K.. 2015. "Tackling the complexity of exact path delay fault grading for path intensive circuits." 2015 20th IEEE European Test Symposium (ETS) , no. : 1-2.

Conference paper
Published: 01 October 2014 in 2014 IEEE 32nd International Conference on Computer Design (ICCD)
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This work proposes a reverse topological ordering for the variables of Zero-suppressed Binary Decision Diagrams (ZBDD) which bounds their size when used to represent the paths of a Directed Acyclic Graph (DAG). Specifically, the size of a ZBDD representing all paths of a DAG is shown to be linear to the number of the edges in the DAG.

ACS Style

Stelios N. Neophytou; Maria K. Michael. Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs. 2014 IEEE 32nd International Conference on Computer Design (ICCD) 2014, 489 -492.

AMA Style

Stelios N. Neophytou, Maria K. Michael. Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs. 2014 IEEE 32nd International Conference on Computer Design (ICCD). 2014; ():489-492.

Chicago/Turabian Style

Stelios N. Neophytou; Maria K. Michael. 2014. "Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs." 2014 IEEE 32nd International Conference on Computer Design (ICCD) , no. : 489-492.

Journal article
Published: 01 August 2014 in Microprocessors and Microsystems
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ACS Style

Stelios Neophytou; Maria K. Michael. Multiple detection test generation with diversified fault partitioning paths. Microprocessors and Microsystems 2014, 38, 585 -597.

AMA Style

Stelios Neophytou, Maria K. Michael. Multiple detection test generation with diversified fault partitioning paths. Microprocessors and Microsystems. 2014; 38 (6):585-597.

Chicago/Turabian Style

Stelios Neophytou; Maria K. Michael. 2014. "Multiple detection test generation with diversified fault partitioning paths." Microprocessors and Microsystems 38, no. 6: 585-597.

Conference paper
Published: 01 December 2013 in 2013 8th IEEE Design and Test Symposium
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Modern multicore systems have multiplied the processing power of computing systems, increasing the potential of solving difficult EDA problems. At the same time, careful decomposition of the problem should be made in order to explore the parallelism without compromising the quality of the result with respect to the existing non-parallel solutions. Test set compaction is one of the major EDA problems that is NP-hard and a crucial component of any ATPG methodology. This paper presents a study on the effect of fault list partitioning on a dynamic test set compaction algorithm that has shown to give very good results when considering the entire fault list. The serial algorithm is executed in different subsets of the considered fault list and the obtained results are evaluated in terms of the compaction achieved as well as the execution time. The experimental results demonstrate that the partitioning technique used highly affects the compaction quality while the execution time is significantly reduced.

ACS Style

Stelios Neophytou; Stavros Hadjitheophanous; Maria K. Michael. On the impact of fault list partitioning in parallel implementations for dynamic test compaction considering multicore systems. 2013 8th IEEE Design and Test Symposium 2013, 1 -6.

AMA Style

Stelios Neophytou, Stavros Hadjitheophanous, Maria K. Michael. On the impact of fault list partitioning in parallel implementations for dynamic test compaction considering multicore systems. 2013 8th IEEE Design and Test Symposium. 2013; ():1-6.

Chicago/Turabian Style

Stelios Neophytou; Stavros Hadjitheophanous; Maria K. Michael. 2013. "On the impact of fault list partitioning in parallel implementations for dynamic test compaction considering multicore systems." 2013 8th IEEE Design and Test Symposium , no. : 1-6.

Conference paper
Published: 01 December 2013 in 2013 8th IEEE Design and Test Symposium
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In test set embedding Built-In Self Test (BIST) schemes a pre-computed test set is embedded into the sequence generated by a hardware generator. These schemes have to evaluate the location of each test pattern in the sequence as fast as possible, in order to test as many as possible candidate configurations of the test pattern generator; this problem is known as the test vector-embedding problem. In this paper we investigate the effect of the size of the test set on the length of the sequence generate of the accumulator structure in order to generate pre-computed test sets and present a method targeting hard-to-detect faults in order to drive down the test generation time.

ACS Style

I. Voyiatzis; S. Neophytou; M. Michaeel; S. Hadjitheophanous; C. Sgouropoulou; C. Efstathiou. Test set embedding into accumulator-generated sequences targeting hard-to-detect faults. 2013 8th IEEE Design and Test Symposium 2013, 1 -2.

AMA Style

I. Voyiatzis, S. Neophytou, M. Michaeel, S. Hadjitheophanous, C. Sgouropoulou, C. Efstathiou. Test set embedding into accumulator-generated sequences targeting hard-to-detect faults. 2013 8th IEEE Design and Test Symposium. 2013; ():1-2.

Chicago/Turabian Style

I. Voyiatzis; S. Neophytou; M. Michaeel; S. Hadjitheophanous; C. Sgouropoulou; C. Efstathiou. 2013. "Test set embedding into accumulator-generated sequences targeting hard-to-detect faults." 2013 8th IEEE Design and Test Symposium , no. : 1-2.

Journal article
Published: 19 October 2012 in Journal of Electronic Testing
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The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs); the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets as well as propagation paths during test application.

ACS Style

Stelios N. Neophytou; Kyriakos Christou; Maria K. Michael. A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits. Journal of Electronic Testing 2012, 28, 843 -856.

AMA Style

Stelios N. Neophytou, Kyriakos Christou, Maria K. Michael. A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits. Journal of Electronic Testing. 2012; 28 (6):843-856.

Chicago/Turabian Style

Stelios N. Neophytou; Kyriakos Christou; Maria K. Michael. 2012. "A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits." Journal of Electronic Testing 28, no. 6: 843-856.

Proceedings article
Published: 01 May 2011 in 2011 Sixteenth IEEE European Test Symposium
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The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs), the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets.

ACS Style

Stelios Neophytou; Kyriakos Christou; Maria K. Michael. An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration. 2011 Sixteenth IEEE European Test Symposium 2011, 141 -146.

AMA Style

Stelios Neophytou, Kyriakos Christou, Maria K. Michael. An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration. 2011 Sixteenth IEEE European Test Symposium. 2011; ():141-146.

Chicago/Turabian Style

Stelios Neophytou; Kyriakos Christou; Maria K. Michael. 2011. "An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration." 2011 Sixteenth IEEE European Test Symposium , no. : 141-146.

Journal article
Published: 01 December 2009 in IEEE Transactions on Computers
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This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements.

ACS Style

Stelios N. Neophytou; Maria K. Michael. Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques. IEEE Transactions on Computers 2009, 59, 301 -316.

AMA Style

Stelios N. Neophytou, Maria K. Michael. Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques. IEEE Transactions on Computers. 2009; 59 (3):301-316.

Chicago/Turabian Style

Stelios N. Neophytou; Maria K. Michael. 2009. "Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques." IEEE Transactions on Computers 59, no. 3: 301-316.

Conference paper
Published: 01 October 2009 in 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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Testing modeled faults multiple times has been shown to increase the likelihood of a test set to detect non-modeled faults, either static or dynamic, when compared to a single detect test set. Test sets that guarantee detecting every modeled fault with at least n different tests are known as n-detect test sets. Moreover, recent investigations examine how different the various tests for a fault should be, in order to further increase their ability in detecting defects. This work proposes a new test generation methodology for multiple-detect (including n-detect) test sets that increases their diversity in terms of the various fault propagation paths excited by the different tests. Specifically, the various tests per modeled fault are guaranteed to propagate the fault effect via different propagation paths. The proposed method can be applied to any linear, to the circuit size, static or dynamic fault model for multiple fault detections, such as the stuck-at or transition delay fault models, and avoids any path or path segment enumeration. Experimental results show increased numbers of propagation paths and non-modeled fault coverages when compared to traditional n-detect test sets.

ACS Style

Stelios Neophytou; Maria K. Michael; Kyriakos Christou. Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning. 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2009, 401 -409.

AMA Style

Stelios Neophytou, Maria K. Michael, Kyriakos Christou. Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning. 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2009; ():401-409.

Chicago/Turabian Style

Stelios Neophytou; Maria K. Michael; Kyriakos Christou. 2009. "Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning." 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , no. : 401-409.

Conference paper
Published: 01 April 2008 in 26th IEEE VLSI Test Symposium (vts 2008)
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While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as n-detect test sets, are of increased quality for a number of common defects in deep sub-micron technologies, n-detect test generation methods usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in an n-detect test set, while preserving the n-detection property, in contrast to any other existing test set relaxation method. The experimental results demonstrate that the number of specified bits in, even compact, n- detect test sets can be significantly reduced without any impact on the n-detect property.

ACS Style

Stelios Neophytou; Maria K. Michael. On the Relaxation of n-detect Test Sets. 26th IEEE VLSI Test Symposium (vts 2008) 2008, 187 -192.

AMA Style

Stelios Neophytou, Maria K. Michael. On the Relaxation of n-detect Test Sets. 26th IEEE VLSI Test Symposium (vts 2008). 2008; ():187-192.

Chicago/Turabian Style

Stelios Neophytou; Maria K. Michael. 2008. "On the Relaxation of n-detect Test Sets." 26th IEEE VLSI Test Symposium (vts 2008) , no. : 187-192.

Proceedings article
Published: 01 March 2008 in 9th International Symposium on Quality Electronic Design (isqed 2008)
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This paper presents two different techniques for relaxing a given test set by maximizing the number of unspecified bits in the test set, without compromising the fault coverage or increasing the test set size. The first method replaces each pattern in the test set with another targeting as few faults as necessary. The second method iterates among faults and enforces detection of a fault only by the test resulting in the largest specified bits reduction. Experimental results show increased reduction rates, even when the input test set has been compacted or already contains unspecified bits, when compared to existing methods. The effectiveness of the proposed methods is demonstrated for two popular test set embedding schemes, using the obtained test sets.

ACS Style

Stelios Neophytou; Maria K. Michael. Two New Methods for Accurate Test Set Relaxation via Test Set Replacement. 9th International Symposium on Quality Electronic Design (isqed 2008) 2008, 827 -831.

AMA Style

Stelios Neophytou, Maria K. Michael. Two New Methods for Accurate Test Set Relaxation via Test Set Replacement. 9th International Symposium on Quality Electronic Design (isqed 2008). 2008; ():827-831.

Chicago/Turabian Style

Stelios Neophytou; Maria K. Michael. 2008. "Two New Methods for Accurate Test Set Relaxation via Test Set Replacement." 9th International Symposium on Quality Electronic Design (isqed 2008) , no. : 827-831.