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Dr. Damien Zander
Research Centre in ICT (CReSTIC), University of Reims, Reims, France

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0 Electrical Engineering
0 Organic Electronics
0 Sustainability
0 electrokinetics
0 Organic semiconductor

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Journal article
Published: 01 October 2012 in Organic Electronics
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ACS Style

R. Ledru; S. Pleutin; B. Grouiez; D. Zander; H. Bejbouji; K. Lmimouni; Dominique Vuillaume. Low frequency dielectric loss of metal/insulator/organic semiconductor junctions in ambient conditions. Organic Electronics 2012, 13, 1916 -1924.

AMA Style

R. Ledru, S. Pleutin, B. Grouiez, D. Zander, H. Bejbouji, K. Lmimouni, Dominique Vuillaume. Low frequency dielectric loss of metal/insulator/organic semiconductor junctions in ambient conditions. Organic Electronics. 2012; 13 (10):1916-1924.

Chicago/Turabian Style

R. Ledru; S. Pleutin; B. Grouiez; D. Zander; H. Bejbouji; K. Lmimouni; Dominique Vuillaume. 2012. "Low frequency dielectric loss of metal/insulator/organic semiconductor junctions in ambient conditions." Organic Electronics 13, no. 10: 1916-1924.

Preprint
Published: 28 April 2012
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The complex admittance of metal/oxide/pentacene thin film junctions is investigated under ambient conditions. At low frequencies, a contribution attributed to proton diffusion through the oxide is seen. This diffusion is shown to be anomalous and is believed to be also at the origin of the bias stress effect observed in organic field effect transistors. At higher frequencies, two dipolar contributions are evidenced, attributed to defects located one at the organic/oxide interface or within the organic, and the other in the bulk of the oxide. These two dipolar responses show different dynamic properties that manifest themselves in the admittance in the form of a Debye contribution for the defects located in the oxide, and of a Cole-Cole contribution for the defects related to the organic.

ACS Style

R. Ledru; S. Pleutin; B. Grouiez; D. Zander; H. Bejbouji; K. Lmimouni; D. Vuillaume. Low Frequency Dielectric Loss of Metal/Insulator/Organic Semiconductor Junctions in Ambient Conditions. 2012, 1 .

AMA Style

R. Ledru, S. Pleutin, B. Grouiez, D. Zander, H. Bejbouji, K. Lmimouni, D. Vuillaume. Low Frequency Dielectric Loss of Metal/Insulator/Organic Semiconductor Junctions in Ambient Conditions. . 2012; ():1.

Chicago/Turabian Style

R. Ledru; S. Pleutin; B. Grouiez; D. Zander; H. Bejbouji; K. Lmimouni; D. Vuillaume. 2012. "Low Frequency Dielectric Loss of Metal/Insulator/Organic Semiconductor Junctions in Ambient Conditions." , no. : 1.

Journal article
Published: 17 June 2005 in Microelectronic Engineering
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We report the characterization of organic field effect transistors fabricated with a novel soluble pentacene precursor. The detail to obtain this novel precursor and the chemical characterization of this precursor are given. The soluble precursor has been deposited on a thin oxide film with lithographically defined electrodes. The determined carrier mobility in organic film is of order of 0.01–0.05 cm2 V−1 s−1.

ACS Style

Damien Zander; Norbert Hoffmann; Kamal Lmimouni; Stéphane Lenfant; Christian Petit; Dominique Vuillaume. Organic field effect transistor based on a novel soluble pentacene precursor and operating at low voltages. Microelectronic Engineering 2005, 80, 394 -397.

AMA Style

Damien Zander, Norbert Hoffmann, Kamal Lmimouni, Stéphane Lenfant, Christian Petit, Dominique Vuillaume. Organic field effect transistor based on a novel soluble pentacene precursor and operating at low voltages. Microelectronic Engineering. 2005; 80 ():394-397.

Chicago/Turabian Style

Damien Zander; Norbert Hoffmann; Kamal Lmimouni; Stéphane Lenfant; Christian Petit; Dominique Vuillaume. 2005. "Organic field effect transistor based on a novel soluble pentacene precursor and operating at low voltages." Microelectronic Engineering 80, no. : 394-397.

Journal article
Published: 18 October 2004 in IEEE Transactions on Nuclear Science
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The effect of high temperature irradiations has been investigated on four types of commercial linear bipolar integrated circuits (ICs) at eight temperatures ranging from 25/spl deg/C to 150/spl deg/C for different total doses at a given dose rate. In agreement with results obtained for individual bipolar transistors, the results show that an optimum irradiation temperature exists that leads to a maximum amount of degradation. Results are compared to low dose rate (LDR) irradiations for ICs with npn and pnp input transistors.

ACS Style

J. Boch; F. Saigne; Ronald Schrimpf; D.M. Fleetwood; R. Cizmarik; D. Zander. Elevated temperature irradiation at high dose rate of commercial linear bipolar ICs. IEEE Transactions on Nuclear Science 2004, 51, 2903 -2907.

AMA Style

J. Boch, F. Saigne, Ronald Schrimpf, D.M. Fleetwood, R. Cizmarik, D. Zander. Elevated temperature irradiation at high dose rate of commercial linear bipolar ICs. IEEE Transactions on Nuclear Science. 2004; 51 (5):2903-2907.

Chicago/Turabian Style

J. Boch; F. Saigne; Ronald Schrimpf; D.M. Fleetwood; R. Cizmarik; D. Zander. 2004. "Elevated temperature irradiation at high dose rate of commercial linear bipolar ICs." IEEE Transactions on Nuclear Science 51, no. 5: 2903-2907.

Journal article
Published: 02 September 2003 in Microelectronics Reliability
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ACS Style

D. Zander; F. Saigne; A. Meinertzhagen; C. Petit. Contribution of oxide traps on defect creation and LVSILC conduction in ultra thin gate oxide devices. Microelectronics Reliability 2003, 43, 1489 -1493.

AMA Style

D. Zander, F. Saigne, A. Meinertzhagen, C. Petit. Contribution of oxide traps on defect creation and LVSILC conduction in ultra thin gate oxide devices. Microelectronics Reliability. 2003; 43 (9-11):1489-1493.

Chicago/Turabian Style

D. Zander; F. Saigne; A. Meinertzhagen; C. Petit. 2003. "Contribution of oxide traps on defect creation and LVSILC conduction in ultra thin gate oxide devices." Microelectronics Reliability 43, no. 9-11: 1489-1493.

Text
Published: 04 August 2003 in Applied Physics Letters
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Interface state creation, after different positive and negative electron direct tunneling injections at elevated temperature are studied. A degradation peak at 100 °C is observed after positive stresses. This peak is attributed to the propensity for boron to be neutralized by hydrogen at this temperature.

ACS Style

D. Zander; J. Boch; F. Saigne; A. Meinertzhagen; O. Simonetti. Effect of boron neutralization on interface state creation after direct tunneling injections at 100 °C in 2,3-nm ultrathin gate oxides. Applied Physics Letters 2003, 83, 926 -927.

AMA Style

D. Zander, J. Boch, F. Saigne, A. Meinertzhagen, O. Simonetti. Effect of boron neutralization on interface state creation after direct tunneling injections at 100 °C in 2,3-nm ultrathin gate oxides. Applied Physics Letters. 2003; 83 (5):926-927.

Chicago/Turabian Style

D. Zander; J. Boch; F. Saigne; A. Meinertzhagen; O. Simonetti. 2003. "Effect of boron neutralization on interface state creation after direct tunneling injections at 100 °C in 2,3-nm ultrathin gate oxides." Applied Physics Letters 83, no. 5: 926-927.

Journal article
Published: 29 January 2002 in Journal of Applied Physics
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It has been shown recently that the low voltage gate current in ultrathin oxide metal–oxide–semiconductor devices is very sensitive to electrical stresses. Therefore it can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements to be used. This paper presents a thorough study of the low voltage gate current variation for different uniformed or localized electrical stress conditions at or above room temperature, and for various oxide thicknesses ranging from 1.2 to 2.5 nm. As it has been proposed recently that this current could be due to electron tunneling through Si/SiO2 interface states, the results obtained in the thicker oxides for the gate current have been compared with the corresponding surface state density variations measured by charge pumping. It is shown that there is no clear relation between low voltage gate current increase after stress and that of surface state density, and that soft or hard oxide breakdown happens when the low voltage current reaches a critical value independently of the stress created interface state density.

ACS Style

A. Meinertzhagen; C. Petit; D. Zander; O. Simonetti; T. Maurel; M. Jourdain. Low voltage stress induced leakage currents and surface states in ultrathin (1.2–2.5 nm) oxides. Journal of Applied Physics 2002, 91, 2123 -2132.

AMA Style

A. Meinertzhagen, C. Petit, D. Zander, O. Simonetti, T. Maurel, M. Jourdain. Low voltage stress induced leakage currents and surface states in ultrathin (1.2–2.5 nm) oxides. Journal of Applied Physics. 2002; 91 (4):2123-2132.

Chicago/Turabian Style

A. Meinertzhagen; C. Petit; D. Zander; O. Simonetti; T. Maurel; M. Jourdain. 2002. "Low voltage stress induced leakage currents and surface states in ultrathin (1.2–2.5 nm) oxides." Journal of Applied Physics 91, no. 4: 2123-2132.

Journal article
Published: 17 July 2001 in Microelectronics Reliability
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It was predicted recently that oxide reliability will limit the oxide scaling at about 2.4 nm and it is known that MOS devices are increasingly required to operate at elevated temperatures. It is therefore important to carefully study the oxide degradation under electrical stress in such oxides at and above room temperature. In this article, it is shown that in 2.3 nm thick oxides, the degradation can be evaluated by monitoring the gate current when the substrate is in depletion and new results are presented on the gradual degradation in these oxides.

ACS Style

D. Zander; C. Petit; F. Saigne; A. Meinertzhagen. High field stress at and above room temperature in 2.3 nm thick oxides. Microelectronics Reliability 2001, 41, 1023 -1026.

AMA Style

D. Zander, C. Petit, F. Saigne, A. Meinertzhagen. High field stress at and above room temperature in 2.3 nm thick oxides. Microelectronics Reliability. 2001; 41 (7):1023-1026.

Chicago/Turabian Style

D. Zander; C. Petit; F. Saigne; A. Meinertzhagen. 2001. "High field stress at and above room temperature in 2.3 nm thick oxides." Microelectronics Reliability 41, no. 7: 1023-1026.

Journal article
Published: 27 February 2001 in Journal of Non-Crystalline Solids
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Oxide reliability is a major concern for deep-submicron technologies as the dielectric thickness decreases. We study the dependence of the interface states and stress induced leakage current increase as a function of electrical stresses at different temperatures. The experiments were performed on ultrathin gate oxide (2.3 nm) metal oxide semi-conductor devices. Charge pumping and gate current as a function of the gate voltage were used to analyze both processes. Stress induced leakage current is still observable when the sensing gate voltage ranges from −1.2 to 0.6 V. We also observe an increase of interface states after different stresses. We show that, for a given stress, the stress induced leakage current increases with the temperature. From the experimental data we show that the general relation of both interface states and stress induced leakage current increases follow a power law with the stress voltage and temperature.

ACS Style

D. Zander; F. Saigne; C. Petit; A. Meinertzhagen. Electrical stress effects on ultrathin (2.3 nm) oxides. Journal of Non-Crystalline Solids 2001, 280, 86 -91.

AMA Style

D. Zander, F. Saigne, C. Petit, A. Meinertzhagen. Electrical stress effects on ultrathin (2.3 nm) oxides. Journal of Non-Crystalline Solids. 2001; 280 (1):86-91.

Chicago/Turabian Style

D. Zander; F. Saigne; C. Petit; A. Meinertzhagen. 2001. "Electrical stress effects on ultrathin (2.3 nm) oxides." Journal of Non-Crystalline Solids 280, no. 1: 86-91.