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Dr. Cesar Zeferino
University of Vale do Itajaí

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Research Keywords & Expertise

0 FPGA
0 Hardware Acceleration
0 Embedded Systems Design
0 Networks-on-Chip
0 Systems-on-Chip

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Networks-on-Chip
FPGA
Systems-on-Chip
Hardware Acceleration

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Journal article
Published: 29 January 2021 in Applied Sciences
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Since the early 2000s, life in cities has changed significantly due to the Internet of Things (IoT). This concept enables developers to integrate different devices collecting, storing, and processing a large amount of data, enabling new services to improve various professional and personal activities. However, privacy issues arise with a large amount of data generated, and solutions based on blockchain technology and smart contract have been developed to address these issues. Nevertheless, several issues must still be taken into account when developing blockchain architectures aimed at the IoT scenario because security flaws still exist in smart contracts, mainly due to the lack of ease when building the code. This article presents a blockchain storage architecture focused on license plate recognition (LPR) systems for smart cities focusing on privacy, performance, and security. The proposed architecture relies on the Ethereum platform. Each smart contract matches the privacy preferences of a license plate to be anonymized through public encryption. The storage of data captured by the LPR system can only be done if the smart contract enables it. However, in the case of motivation foreseen by the legislation, a competent user can change the smart contract and enable the storage of the data captured by the LPR system. Experimental results show that the performance of the proposed architecture is satisfactory, regarding the scalability of the built private network. Furthermore, tests on our smart contract using security and structure analysis tools on the developed script demonstrate that our solution is fraud-proof. The results obtained in all experiments bring evidence that our architecture is feasible to be used in real scenarios.

ACS Style

Iago Sestrem Ochôa; Valderi Reis Quietinho Leithardt; Leonardo Calbusch; Juan De Paz Santana; Wemerson Delcio Parreira; Laio Oriel Seman; Cesar Zeferino. Performance and Security Evaluation on a Blockchain Architecture for License Plate Recognition Systems. Applied Sciences 2021, 11, 1255 .

AMA Style

Iago Sestrem Ochôa, Valderi Reis Quietinho Leithardt, Leonardo Calbusch, Juan De Paz Santana, Wemerson Delcio Parreira, Laio Oriel Seman, Cesar Zeferino. Performance and Security Evaluation on a Blockchain Architecture for License Plate Recognition Systems. Applied Sciences. 2021; 11 (3):1255.

Chicago/Turabian Style

Iago Sestrem Ochôa; Valderi Reis Quietinho Leithardt; Leonardo Calbusch; Juan De Paz Santana; Wemerson Delcio Parreira; Laio Oriel Seman; Cesar Zeferino. 2021. "Performance and Security Evaluation on a Blockchain Architecture for License Plate Recognition Systems." Applied Sciences 11, no. 3: 1255.

Review
Published: 31 December 2020 in Journal of Sensor and Actuator Networks
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Cryptography is considered indispensable among security measures applied to data concerning insecure means of transmission. Among various existent algorithms on asymmetric cryptography, we may cite Elliptic Curve Cryptography (ECC), which has been widely used due to its security level and reduced key sizes. When compared to Rivest, Shamir and Adleman (RSA), for example, ECC can maintain security levels with a shorter key. Elliptic Curve Point Multiplication (ECPM) is the main function in ECC, and is the component with the highest hardware cost. Lots of ECPM implementations have been applied on hardware targeting the acceleration of its calculus. This article presents a systematic review of literature on ECPM implementations on both Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC). The obtained results show which methods and technologies have been used to implement ECPM on hardware and present some findings of the choices available to the hardware designers.

ACS Style

Arielle Verri Lucca; Guilherme Mariano Sborz; Valderi Leithardt; Marko Beko; Cesar Albenes Zeferino; Wemerson Parreira. A Review of Techniques for Implementing Elliptic Curve Point Multiplication on Hardware. Journal of Sensor and Actuator Networks 2020, 10, 3 .

AMA Style

Arielle Verri Lucca, Guilherme Mariano Sborz, Valderi Leithardt, Marko Beko, Cesar Albenes Zeferino, Wemerson Parreira. A Review of Techniques for Implementing Elliptic Curve Point Multiplication on Hardware. Journal of Sensor and Actuator Networks. 2020; 10 (1):3.

Chicago/Turabian Style

Arielle Verri Lucca; Guilherme Mariano Sborz; Valderi Leithardt; Marko Beko; Cesar Albenes Zeferino; Wemerson Parreira. 2020. "A Review of Techniques for Implementing Elliptic Curve Point Multiplication on Hardware." Journal of Sensor and Actuator Networks 10, no. 1: 3.

Conference paper
Published: 23 November 2020 in Anais Estendidos do X Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC Estendido 2020)
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The growing use of computer vision applications has increased the demand for efficient image processing implementations. These applications have constraints that, in some cases, can only be met by dedicated hardware implementations. This work presents architectures that apply approximate computing techniques to improve efficiency and scalability for implementing digital image filters on FPGA. These architectures were implemented as hardware accelerators for an embedded processor in an FPGA-based System-on-Chip. The results show that the use of approximate computing techniques can reduce costs without affecting results for the target application, which is an essential feature for further acceleration using parallel processing on hardware.

ACS Style

Guilherme Sborz; Felipe Viel; Cesar Zeferino. Architectural Exploration of an FPGA-based Hardware Accelerator for the Gaussian Filter using Approximate Computing. Anais Estendidos do X Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC Estendido 2020) 2020, 186 -191.

AMA Style

Guilherme Sborz, Felipe Viel, Cesar Zeferino. Architectural Exploration of an FPGA-based Hardware Accelerator for the Gaussian Filter using Approximate Computing. Anais Estendidos do X Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC Estendido 2020). 2020; ():186-191.

Chicago/Turabian Style

Guilherme Sborz; Felipe Viel; Cesar Zeferino. 2020. "Architectural Exploration of an FPGA-based Hardware Accelerator for the Gaussian Filter using Approximate Computing." Anais Estendidos do X Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC Estendido 2020) , no. : 186-191.

Conference paper
Published: 23 November 2020 in Anais Estendidos do X Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC Estendido 2020)
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Computer vision systems have several stages, and one of the operators used in these systems is the edge detection filter. High-performance computing is required in many applications and stages of computer vision systems, and many designs use FPGA technology to improve performance and decrease power consumption. In this context, this work presents an analysis of five edge detection filters synthesized to FPGA, including Laplacian, Roberts, Prewitt, Sobel, and Canny. In the experiments, we compared the hardware implementations with software versions to identify the impact of fixed-point representation on the quality of the output images. We have also assessed metrics regarding performance, silicon costs, and energy consumption. The results obtained show that the Laplacian filter has the lowest costs, while the Canny operator provides the best output image at the price of much higher silicon costs and energy consumption.

ACS Style

Douglas Santos; Daniel Zolett; Mateus Belli; Felipe Viel; Cesar Zeferino. An Analysis of the Implementation of Edge Detection Operators in FPGA. Anais Estendidos do X Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC Estendido 2020) 2020, 163 -167.

AMA Style

Douglas Santos, Daniel Zolett, Mateus Belli, Felipe Viel, Cesar Zeferino. An Analysis of the Implementation of Edge Detection Operators in FPGA. Anais Estendidos do X Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC Estendido 2020). 2020; ():163-167.

Chicago/Turabian Style

Douglas Santos; Daniel Zolett; Mateus Belli; Felipe Viel; Cesar Zeferino. 2020. "An Analysis of the Implementation of Edge Detection Operators in FPGA." Anais Estendidos do X Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC Estendido 2020) , no. : 163-167.

Journal article
Published: 14 October 2020 in Applied Sciences
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Exoskeletons are wearable mobile robots that combine various technologies to enable limb movement with greater strength and endurance, being used in several application areas, such as industry and medicine. In this context, this paper presents the development of a hybrid control method for exoskeletons, combining admission and impedance control based on electromyographic input signals. A proof of concept of a robotic arm with two degrees of freedom, mimicking the functions of a human’s upper limb, was built to evaluate the proposed control system. Through tests that measured the discrepancy between the angles of the human joint and the joint of the exoskeleton, it was possible to determine that the system remained within an acceptable error range. The average error is lower than 4.3%, and the robotic arm manages to mimic the movements of the upper limbs of a human in real-time.

ACS Style

Lucas D. L. Da Silva; Thiago F. Pereira; Valderi R. Q. Leithardt; Laio O. Seman; Cesar A. Zeferino. Hybrid Impedance-Admittance Control for Upper Limb Exoskeleton Using Electromyography. Applied Sciences 2020, 10, 7146 .

AMA Style

Lucas D. L. Da Silva, Thiago F. Pereira, Valderi R. Q. Leithardt, Laio O. Seman, Cesar A. Zeferino. Hybrid Impedance-Admittance Control for Upper Limb Exoskeleton Using Electromyography. Applied Sciences. 2020; 10 (20):7146.

Chicago/Turabian Style

Lucas D. L. Da Silva; Thiago F. Pereira; Valderi R. Q. Leithardt; Laio O. Seman; Cesar A. Zeferino. 2020. "Hybrid Impedance-Admittance Control for Upper Limb Exoskeleton Using Electromyography." Applied Sciences 10, no. 20: 7146.

Journal article
Published: 17 September 2020 in Electronics
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Smart environments are pervasive computing systems that provide higher comfort levels on daily routines throughout interactions among smart sensors and embedded computers. The lack of privacy within these interactions can lead to the exposure of sensitive data. We present PRIPRO (PRIvacy PROfiles), a management tool that includes an Android application that acts on the user’s smartphone by allowing or blocking resources according to the context, in order to address this issue. Back-end web server processes and imposes a protocol according to the conditions that the user selected beforehand. The experimental results show that the proposed solution successfully communicates with the Android Device Administration framework, and the device appropriately reacts to the expected set of permissions imposed according to the user’s profile with low response time and resource usage.

ACS Style

Jonas Cesconetto; Luís Augusto Silva; Fabricio Bortoluzzi; María Navarro-Cáceres; Cesar A. Zeferino; Valderi R. Q. Leithardt. PRIPRO—Privacy Profiles: User Profiling Management for Smart Environments. Electronics 2020, 9, 1519 .

AMA Style

Jonas Cesconetto, Luís Augusto Silva, Fabricio Bortoluzzi, María Navarro-Cáceres, Cesar A. Zeferino, Valderi R. Q. Leithardt. PRIPRO—Privacy Profiles: User Profiling Management for Smart Environments. Electronics. 2020; 9 (9):1519.

Chicago/Turabian Style

Jonas Cesconetto; Luís Augusto Silva; Fabricio Bortoluzzi; María Navarro-Cáceres; Cesar A. Zeferino; Valderi R. Q. Leithardt. 2020. "PRIPRO—Privacy Profiles: User Profiling Management for Smart Environments." Electronics 9, no. 9: 1519.

Journal article
Published: 23 July 2020 in IEEE Geoscience and Remote Sensing Letters
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Hyperspectral images (HSIs) are the images that have a high spectral resolution with hundreds of bands. HSIs are widely used in the precise identification and classification of the materials and surfaces. However, they have a low spatial resolution caused by the limited capacity of the sensors responsible for capturing the images. In view of this, the preprocessing techniques are used to increase the spatial resolution of the HSIs and enable greater precision in the subsequent processing stages. This letter presents the development of a hardware accelerator specially designed to process a pansharpening algorithm that fuses the hyperspectral and panchromatic images to produce a high spatial resolution HSI. The experimental results demonstrate that the processor is energy-efficient and can be used for onboard processing in a small spacecraft, such as the satellites.

ACS Style

Felipe Viel; Wemerson Delcio Parreira; Altamiro Amadeu Susin; Cesar Albenes Zeferino. A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images. IEEE Geoscience and Remote Sensing Letters 2020, 1 -5.

AMA Style

Felipe Viel, Wemerson Delcio Parreira, Altamiro Amadeu Susin, Cesar Albenes Zeferino. A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images. IEEE Geoscience and Remote Sensing Letters. 2020; (99):1-5.

Chicago/Turabian Style

Felipe Viel; Wemerson Delcio Parreira; Altamiro Amadeu Susin; Cesar Albenes Zeferino. 2020. "A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images." IEEE Geoscience and Remote Sensing Letters , no. 99: 1-5.

Journal article
Published: 25 May 2020 in IEEE Latin America Transactions
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Internet of Things (IoT) is an emerging area in which we expect to have billions of devices connected to the Internet by 2020. IoT applications can offer many benefits to environments, society, and the economy through the interconnection and cooperation of smart objects. However, there are many privacy challenges, such as authentication, authorization, and confidentiality of personal data. With this in mind, we developed a solution for dynamically managing user profiles according to the characteristics of each environment. This solution is a module of a middleware named (Ubiquitous Privacy) and traces the frequency of the user in the environment to update its profile according to the environment's rules. The implemented module was validated using scripts that perform probabilistic simulation and user authentication. From the rules assigned to the simulated environments, it was possible to confirm the high adaptability of the implementation. We also verified that it could be easily adjusted to any IoT environment that wants to treat the authentication and privacy of environments and users.

ACS Style

Valderi Leithardt; Douglas Santos; Luis Silva; Felipe Viel; Cesar Zeferino; Jorge Silva. A Solution for Dynamic Management of User Profiles in IoT Environments. IEEE Latin America Transactions 2020, 18, 1193 -1199.

AMA Style

Valderi Leithardt, Douglas Santos, Luis Silva, Felipe Viel, Cesar Zeferino, Jorge Silva. A Solution for Dynamic Management of User Profiles in IoT Environments. IEEE Latin America Transactions. 2020; 18 (07):1193-1199.

Chicago/Turabian Style

Valderi Leithardt; Douglas Santos; Luis Silva; Felipe Viel; Cesar Zeferino; Jorge Silva. 2020. "A Solution for Dynamic Management of User Profiles in IoT Environments." IEEE Latin America Transactions 18, no. 07: 1193-1199.

Journal article
Published: 17 May 2020 in Sensors
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The evolution of computing devices and ubiquitous computing has led to the development of the Internet of Things (IoT). Smart Grids (SGs) stand out among the many applications of IoT and comprise several embedded intelligent technologies to improve the reliability and the safety of power grids. SGs use communication protocols for information exchange, such as the Open Smart Grid Protocol (OSGP). However, OSGP does not support the integration with devices compliant with the Constrained Application Protocol (CoAP), a communication protocol used in conventional IoT systems. In this sense, this article presents an efficient software interface that provides integration between OSGP and CoAP. The results obtained demonstrate the effectiveness of the proposed solution, which presents low communication overhead and enables the integration between IoT and SG systems.

ACS Style

Felipe Viel; Luis Augusto Silva; Valderi Reis Quietinho Leithardt; Juan Francisco De Paz Santana; Raimundo Celeste Ghizoni Teive; Cesar Albenes Zeferino. An Efficient Interface for the Integration of IoT Devices with Smart Grids. Sensors 2020, 20, 2849 .

AMA Style

Felipe Viel, Luis Augusto Silva, Valderi Reis Quietinho Leithardt, Juan Francisco De Paz Santana, Raimundo Celeste Ghizoni Teive, Cesar Albenes Zeferino. An Efficient Interface for the Integration of IoT Devices with Smart Grids. Sensors. 2020; 20 (10):2849.

Chicago/Turabian Style

Felipe Viel; Luis Augusto Silva; Valderi Reis Quietinho Leithardt; Juan Francisco De Paz Santana; Raimundo Celeste Ghizoni Teive; Cesar Albenes Zeferino. 2020. "An Efficient Interface for the Integration of IoT Devices with Smart Grids." Sensors 20, no. 10: 2849.

Preprint
Published: 16 January 2020
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The evolution and miniaturization of the technologies for processing, storage, and communication have enabled computer systems to process a high volume of information and make decisions without human intervention. Within this context, several systems architectures and models have gained prominences, such as the Internet of Things (IoT) and Smart Grids (SGs). SGs use communication protocols to exchange information, among which the Open Smart Grid Protocol (OSGP) stands out. In contrast, this protocol does not have integration support with IoT systems that use some already consolidated communication protocols, such as the Constrained Application Protocol (CoAP). Thus, this work develops the integration of the protocols OSGP and CoAP to allow the communication between conventional IoT systems and systems dedicated to SGs. Results demonstrate the effectiveness of this integration, with the minimum impact on the flow of commands and data, making possible the use of the developed CoAP-OSGP Interface for Internet of Things (COIIoT).

ACS Style

Felipe Viel; Luis Augusto Silva; Valderi Leithardt; Gabriel Villarubia González; Raimundo Celeste Ghizoni Teive; Cesar Albenes Zeferino. COIIoT - An Interface between CoAP and OSGP Protocols for the Integration of Internet of Things Devices with Smart Grids. 2020, 1 .

AMA Style

Felipe Viel, Luis Augusto Silva, Valderi Leithardt, Gabriel Villarubia González, Raimundo Celeste Ghizoni Teive, Cesar Albenes Zeferino. COIIoT - An Interface between CoAP and OSGP Protocols for the Integration of Internet of Things Devices with Smart Grids. . 2020; ():1.

Chicago/Turabian Style

Felipe Viel; Luis Augusto Silva; Valderi Leithardt; Gabriel Villarubia González; Raimundo Celeste Ghizoni Teive; Cesar Albenes Zeferino. 2020. "COIIoT - An Interface between CoAP and OSGP Protocols for the Integration of Internet of Things Devices with Smart Grids." , no. : 1.

Journal article
Published: 09 December 2019 in Sensors
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Reducing component size and increasing the operating frequency of integrated circuits makes the Systems-on-Chip (SoCs) more susceptible to faults. Faults can cause errors, and errors can be propagated and lead to a system failure. SoCs employing many cores rely on a Network-on-Chip (NoC) as the interconnect architecture. In this context, this study explores alternatives to implement the flow regulation, routing, and arbitration controllers of an NoC router aiming at minimizing error propagation. For this purpose, a router with Finite-State Machine (FSM)-based controllers was developed targeting low use of logical resources and design flexibility for implementation in FPGA devices. We elaborated and compared the synthesis and simulation results of architectures that vary their controllers on Moore and Mealy FSMs, as well as the Triple Modular Redundancy (TMR) hardening application. Experimental results showed that the routing controller was the most critical one and that migrating a Moore to a Mealy controller offered a lower error propagation rate and higher performance than the application of TMR. We intended to use the proposed router architecture to integrate cores in a fault-tolerant NoC-based system for data processing in harsh environments, such as in space applications.

ACS Style

Douglas R. Melo; Cesar A. Zeferino; Luigi DiLillo; Eduardo A. Bezerra. Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design. Sensors 2019, 19, 5416 .

AMA Style

Douglas R. Melo, Cesar A. Zeferino, Luigi DiLillo, Eduardo A. Bezerra. Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design. Sensors. 2019; 19 (24):5416.

Chicago/Turabian Style

Douglas R. Melo; Cesar A. Zeferino; Luigi DiLillo; Eduardo A. Bezerra. 2019. "Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design." Sensors 19, no. 24: 5416.

Conference paper
Published: 01 November 2019 in 2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC)
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User-interactions with IoT appliances usually occur via raw interfaces, mobile devices, or desktop computers. Besides, during the handling of some devices, the user may be better served by a rich and contextualized embedded interface. This paper presents a distributed architecture for the delivery of graphical web interfaces in constrained IoT devices with an ultra-thin client approach. A strategy for the development of rich and contextualized interfaces for IoT constrained devices is outlined, envisioning a future with the tactile internet. The proposed architecture employs hardware acceleration, fog computing, virtual IoT devices, screen virtualization, and proxy-based web browsing. To validate the architecture, we have implemented a prototype of a constrained smartwatch with a proxy-based web browser. The experimental results show that the proposed architecture is suitable for devices and networks with constrained resources, allowing the display of web apps graphical representations with the potential to offer soft and low-latency user interactions.

ACS Style

Luiz Fernando Heidrich Duarte; Cesar Zeferino; Raimundo Celeste Ghizoni Teive. An Architecture for Delivering Graphical Web Applications in Constrained IoT Devices. 2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC) 2019, 1 -8.

AMA Style

Luiz Fernando Heidrich Duarte, Cesar Zeferino, Raimundo Celeste Ghizoni Teive. An Architecture for Delivering Graphical Web Applications in Constrained IoT Devices. 2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC). 2019; ():1-8.

Chicago/Turabian Style

Luiz Fernando Heidrich Duarte; Cesar Zeferino; Raimundo Celeste Ghizoni Teive. 2019. "An Architecture for Delivering Graphical Web Applications in Constrained IoT Devices." 2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC) , no. : 1-8.

Data article
Published: 28 October 2019 in Data in Brief
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This article presents data from an extensive set of simulation-based experiments to compare the performance of on-chip communication architectures. These experiments were performed using the RedScarf simulation environment [1], which is described in the article entitled ‘RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip’ [2]. In the experiments presented here, several intra-chip communication architectures were compared under different traffic patterns. Latency, jitter, and throughput metrics were collected. Data is useful for researchers investigating on-chip communication architectures who need baseline data for comparison.

ACS Style

Eduardo Alves da Silva; Márcio Kreutz; Cesar Albenes Zeferino. Experimental data from the simulation of on-chip communication architectures using RedScarf simulation environment. Data in Brief 2019, 27, 104725 .

AMA Style

Eduardo Alves da Silva, Márcio Kreutz, Cesar Albenes Zeferino. Experimental data from the simulation of on-chip communication architectures using RedScarf simulation environment. Data in Brief. 2019; 27 ():104725.

Chicago/Turabian Style

Eduardo Alves da Silva; Márcio Kreutz; Cesar Albenes Zeferino. 2019. "Experimental data from the simulation of on-chip communication architectures using RedScarf simulation environment." Data in Brief 27, no. : 104725.

Journal article
Published: 21 August 2019 in Journal of Systems Architecture
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The design space of Networks-on-Chip (NoCs) comprises a large number of architectural parameters. To comply with the performance requirements of target applications, NoC-based system designers need to employ tools to assess the impact of each parameter on the NoC and the performance of the application. In view of this, this paper presents a simulation environment named RedScarf, which was developed to facilitate the design space exploration of NoCs. RedScarf integrates a graphical user interface and a set of tools that automate the process of configuring and evaluating the network characteristics. By providing resources like multi-platform and multi-thread execution, among others, RedScarf is a powerful tool for Research and Education on NoCs. This work describes the RedScarf architecture and tools, and demonstrates by means of experiments how it can aid a designer in the task of assessing the performance of on-chip interconnect architectures.

ACS Style

Eduardo A. Da Silva; Márcio E. Kreutz; Cesar A. Zeferino. RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip. Journal of Systems Architecture 2019, 99, 101633 .

AMA Style

Eduardo A. Da Silva, Márcio E. Kreutz, Cesar A. Zeferino. RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip. Journal of Systems Architecture. 2019; 99 ():101633.

Chicago/Turabian Style

Eduardo A. Da Silva; Márcio E. Kreutz; Cesar A. Zeferino. 2019. "RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip." Journal of Systems Architecture 99, no. : 101633.

Conference paper
Published: 01 August 2019 in 2019 17th International Conference on Privacy, Security and Trust (PST)
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Over the past decade, smart crime-fighting solutions have been adopted by the major cities around the world. In this context, license plate recognition (LPR) systems have been used by public safety forces to monitor vehicle movement. However, current systems store vehicle location data indistinctly, without differentiating vehicles that are under criminal investigation from those that are not. This monitoring may be used to infer personal data about the owner of the vehicle, resulting in a violation of privacy by disregarding data protection laws. This paper presents a study about the use of technologies to ensure privacy in the Internet of Things and proposes a model to protect data collected by LPR systems. Our solution uses private blockchains regulated by smart contracts to ensure that the storage of data complies with current data protection laws.

ACS Style

Iago Ochoa; Leonardo Calbusch; Karize Viecelli; Juan F. De Paz; Valderi Reis Quietinho Leithardt; Cesar Zeferino. Privacy in the Internet of Things: A Study to Protect User's Data in LPR Systems Using Blockchain. 2019 17th International Conference on Privacy, Security and Trust (PST) 2019, 1 -5.

AMA Style

Iago Ochoa, Leonardo Calbusch, Karize Viecelli, Juan F. De Paz, Valderi Reis Quietinho Leithardt, Cesar Zeferino. Privacy in the Internet of Things: A Study to Protect User's Data in LPR Systems Using Blockchain. 2019 17th International Conference on Privacy, Security and Trust (PST). 2019; ():1-5.

Chicago/Turabian Style

Iago Ochoa; Leonardo Calbusch; Karize Viecelli; Juan F. De Paz; Valderi Reis Quietinho Leithardt; Cesar Zeferino. 2019. "Privacy in the Internet of Things: A Study to Protect User's Data in LPR Systems Using Blockchain." 2019 17th International Conference on Privacy, Security and Trust (PST) , no. : 1-5.

Conference paper
Published: 01 May 2019 in 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
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Hyperspectral images are a widely used remote sensing technique. These images are three-dimensional data structures, where the x and y axes contain spatial information and the z-axis contains spectral information or image bands. Usually, these bands can reach the order of hundreds, generating a considerable amount of information. Due to storage limitations and communication bandwidth, the use of compression techniques becomes essential. For spatial applications, a standard commonly used in the literature is CCSDS 123, developed by the Consultative Committee for Space Data Systems, which describes the algorithm for lossless compression of hyperspectral images. In this context, we implemented the prediction stage of the CCSDS 123 algorithm in the Xilinx Zynq-7000 FPGA. The developed processor provides a good trade-off to meet real-time requirements at low-cost.

ACS Style

Lucas M. V. Pereira; Douglas A. Santos; Cesar A. Zeferino; Douglas R. Melo. A Low-Cost Hardware Accelerator for CCSDS 123 Predictor in FPGA. 2019 IEEE International Symposium on Circuits and Systems (ISCAS) 2019, 1 -5.

AMA Style

Lucas M. V. Pereira, Douglas A. Santos, Cesar A. Zeferino, Douglas R. Melo. A Low-Cost Hardware Accelerator for CCSDS 123 Predictor in FPGA. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). 2019; ():1-5.

Chicago/Turabian Style

Lucas M. V. Pereira; Douglas A. Santos; Cesar A. Zeferino; Douglas R. Melo. 2019. "A Low-Cost Hardware Accelerator for CCSDS 123 Predictor in FPGA." 2019 IEEE International Symposium on Circuits and Systems (ISCAS) , no. : 1-5.

Proceedings article
Published: 01 March 2019 in 2019 IEEE Latin American Test Symposium (LATS)
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The constant reduction in the components size in integrated circuits and the increase of the operating frequency make Systems-on-Chip (SoCs) more vulnerable to noise and other interference phenomena. Such phenomena can lead to faults, which generate errors that may result in a system crash. SoCs with dozens of cores use Networks-on-Chip as their interconnection architecture. In this context, this work presents an analysis of the error propagation in a parameterizable router architecture that allows different combinations of input and output controllers, data width and buffers depth. The router has been described focusing on design flexibility and low logical resource occupation. We elaborated different combinations of the router architecture and evaluated the error propagation by means of Single Event Upset fault injections. The synthesis results presented a reasonable increase in term of logical elements when applying wider data representations, and combinations using Mealy finite state machines in the routing component had the lowest error propagation rate at a price of a small degradation in the maximum operating frequency.

ACS Style

Douglas Rossi De Melo; Cesar Albenes Zeferino; Luigi Dilillo; Eduardo Augusto Bezerra. Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. 2019 IEEE Latin American Test Symposium (LATS) 2019, 1 -6.

AMA Style

Douglas Rossi De Melo, Cesar Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra. Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. 2019 IEEE Latin American Test Symposium (LATS). 2019; ():1-6.

Chicago/Turabian Style

Douglas Rossi De Melo; Cesar Albenes Zeferino; Luigi Dilillo; Eduardo Augusto Bezerra. 2019. "Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router." 2019 IEEE Latin American Test Symposium (LATS) , no. : 1-6.

Conference paper
Published: 01 January 2019 in Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19
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ACS Style

Guilherme A. M. Sborz; Guilherme A. Pohl; Felipe Viel; Cesar A. Zeferino. A custom processor for an FPGA-based platform for automatic license plate recognition. Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19 2019, 15 .

AMA Style

Guilherme A. M. Sborz, Guilherme A. Pohl, Felipe Viel, Cesar A. Zeferino. A custom processor for an FPGA-based platform for automatic license plate recognition. Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19. 2019; ():15.

Chicago/Turabian Style

Guilherme A. M. Sborz; Guilherme A. Pohl; Felipe Viel; Cesar A. Zeferino. 2019. "A custom processor for an FPGA-based platform for automatic license plate recognition." Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19 , no. : 15.

Conference paper
Published: 01 January 2019 in Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19
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ACS Style

Lucas A. Martins; Guilherme A. M. Sborz; Felipe Viel; Cesar A. Zeferino. An SVM-based hardware accelerator for onboard classification of hyperspectral images. Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19 2019, 18 .

AMA Style

Lucas A. Martins, Guilherme A. M. Sborz, Felipe Viel, Cesar A. Zeferino. An SVM-based hardware accelerator for onboard classification of hyperspectral images. Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19. 2019; ():18.

Chicago/Turabian Style

Lucas A. Martins; Guilherme A. M. Sborz; Felipe Viel; Cesar A. Zeferino. 2019. "An SVM-based hardware accelerator for onboard classification of hyperspectral images." Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design - SBCCI '19 , no. : 18.

Conference paper
Published: 01 November 2018 in 2018 13th IEEE International Conference on Industry Applications (INDUSCON)
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This work presents a simulation model for point-to-point transmission of encrypted data using the application layer of Open Smart Grid Protocol (OSGP). The simulation aims to verify the integrity of the data transmitted from one point to another using Power Line Communication (PLC). The simulation model was developed in MATLAB and uses RSA, AES, RC-6, and 3-DES cryptographies to encode data. Data transmission uses PLC technique with Gaussian Minimmum Shift Key (GMSK) modulation. Results demonstrate that it is possible to use the OSGP protocol in the application layer with different criteria, which can be used according to the data size. It was applied a Additive White Gaussian Noise (AWGN) in the transmission to simulate the effects that exist in a real network. The experiments demonstrate that RC-6 outperforms the other cryptographic algorithms, presenting the smallest execution time, with low memory requirements.

ACS Style

Iago Sestrem Ochôa; Valderi Reis Quietinho Leithardt; Cesar Zeferino; Jorge Sa Silva. Data Transmission Performance Analysis with Smart Grid Protocol and Cryptography Algorithms. 2018 13th IEEE International Conference on Industry Applications (INDUSCON) 2018, 482 -486.

AMA Style

Iago Sestrem Ochôa, Valderi Reis Quietinho Leithardt, Cesar Zeferino, Jorge Sa Silva. Data Transmission Performance Analysis with Smart Grid Protocol and Cryptography Algorithms. 2018 13th IEEE International Conference on Industry Applications (INDUSCON). 2018; ():482-486.

Chicago/Turabian Style

Iago Sestrem Ochôa; Valderi Reis Quietinho Leithardt; Cesar Zeferino; Jorge Sa Silva. 2018. "Data Transmission Performance Analysis with Smart Grid Protocol and Cryptography Algorithms." 2018 13th IEEE International Conference on Industry Applications (INDUSCON) , no. : 482-486.