Ytterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, which is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO/sub 2/ gate dielectric, and HaN/TaN metal gate. The YbSi/sub 2 - x/ silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I/sub on//l/sub off/ ratio of /spl sim/10/sup 7/ and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi/sub 2 - x//Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.

Power consumption is the most difficult challenge for CMOS integrated circuits. Here, we demonstrate experimentally a novel steep turn-on pMOSFET for low-voltage operation for the first time, which exhibits 5-60 mV/decade SS, wide voltage range for , sturdy SS at 85°C, faster transistor turn-on at above threshold voltage, and lower off-state leakage by greater than three orders of magnitude. Such improved leakage current is crucial to decrease the OFF-state leakage current in sub-1X nm CMOS. This was achieved using ferroelectric high-κ ZrHfO gate dielectric pMOSFET.

The power consumption of capacitor leakage current, increase of the capacitor aspect ratio, and lack of higher dielectric constant (κ) material are the difficult challenges to downscaling dynamic random access memory (DRAM). This letter reports a new one-transistor ferroelectric-MOSFET (1T FeMOS) device that displays DRAM functions of a 5 ns switching time, 10¹² on/off endurance cycles, and 30 times on/off retention windows at 5 s and 85 °C. A simple 1T process and a considerably low OFF-state leakage of 3×10^-12 A/μm were achieved. This novel device was achieved by applying ferroelectric ZrHfO gate dielectric to a p-MOSFET, which is fully compatible with existing high-κ CMOS processing.

An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied. The surface SiH4 annealing was implemented prior to HfO2 deposition. X-ray photoelectron spectroscopy analysis results show that the SiH4 surface passivation can greatly prevent the formation of unstable germanium oxide at the surface and suppress the Ge out-diffusion after the HfO2 deposition. The electrical measurement shows that an equivalent oxide thickness of 13.5Å and a leakage current of 1.16×10−5A∕cm2 at 1V gate bias was achieved for TaN∕HfO2∕Ge MOS capacitors with the SiH4 surface treatment.

Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.