The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using nulling resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-/spl mu/m process are found to be in good agreement with the expected results.

Smart homes/offices based on Wireless Sensor Networks (WSNs) can provide an assisted living and working environment to the users. In these applications, the distributed network nodes are made up of low-power low-cost high-energy-efficient electronic platforms equipped with sensors, microcontroller, radio and antenna, able to periodically sense, receive, store, pre-process and transmit ambient data to a remote host station. Conventional nodes are usually supplied by batteries, resulting in a significant limitation to the life time and to the maximum number of deployable devices. To meet the demand of next Internet of Things (IoT) applications, requiring a vast plurality of interconnected wireless network nodes, this paper presents the design and implementation of a WSN platform whose nodes are energetically autonomous thanks to an embedded photovoltaic (PV) panel associated to a rechargeable battery and a power-efficient design with optimized power-management strategy. The implemented node is able to harvest indoor ambient light starting from 100 lux and, according to the available energy, adaptively sets the sensors acquisition and RF transmission rate. Moreover, it provides long-distance data transmission with air data rate from 1 to 500 kbps. The WSN node device is implemented on an 8.6 × 5.4-cm2 flexible PCB, being therefore amenable to conform even to curved surfaces. Comparison with commercial IoT nodes reveals a significant improvement in the state of the art.

A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented. The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed a CMOS OTA in a 0.35- μm technology that occupies only 4.4·10 ^-3 mm ² , is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 mV/μs with the 200 pF load. Comparison with prior art shows an improvement factor in the figures of merit higher than 5.