In this work, we present the results of an investigation into the effectiveness of varying ammonium sulphide concentrations in the passivation of -type and -type . Samples were degreased and immersed in aqueous solutions of concentrations 22%, 10%, 5%, or 1% for 20 min at 295 K, immediately prior to atomic layer deposition of . Multi-frequency capacitance-voltage (C-V) results on capacitor structures indicate that the lowest frequency dispersion over the bias range examined occurs for -type and -type devices treated with the solution. The deleterious effect on device behavior of increased ambient exposure time after removal from solution is also presented. Estimations of the interface state defect density for the optimum passivated devices extracted using an approximation to the conductance method, and also extracted using the temperature-modified high-low frequency C-V method, indicate that the same defect is present over -type and -type devices having an integrated of with the peak density positioned in the middle of the band gap at approximately 0.37 eV (±0.03 eV) from the valence band edge. Both methods used for extracting show very good agreement, providing evidence to support that the conductance method can be applied to devices incorporating high- oxides on .
Electrical properties of metal-oxide-semiconductor capacitors using atomic layer deposited HfO2 on n-type GaAs or InxGa1−xAs (x=0.53, 0.30, 0.15) epitaxial layers were investigated. Capacitance-voltage (CV) measurements indicated large temperature and frequency dispersion at positive gate bias in devices using n-type GaAs and low In content (x=0.30, 0.15) InxGa1−xAs layers, which is significantly reduced for devices using In0.53Ga0.47As. For In0.53Ga0.47As devices, the CV response at negative gate bias is most likely characteristic of an interface state response and may not be indicative of true inversion. The conductance technique on Pd/HfO2/In0.53Ga0.47As/InP shows reductions in interface state densities by In0.53Ga0.47As surface passivation and forming gas annealing (325 °C).
In this work, we present the results of an investigation into charge trapping in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOS capacitors), which is analysed using the hysteresis exhibited in the capacitance-voltage (C-V) response. The availability of both n and p doped In0.53Ga0.47As epitaxial layers allows the investigation of both hole and electron trapping in the bulk of HfO2 and Al2O3 films formed using atomic layer deposition (ALD). The HfO2/In0.53Ga0.47As and Al2O3/In0.53Ga0.47As MOS capacitors exhibit an almost reversible trapping behaviour, where the density of trapped charge is of a similar level to high-k/In0.53Ga0.47As interface state density, for both electrons and holes in the HfO2 and Al2O3 films. The experimental results demonstrate that the magnitude of the C-V hysteresis increases significantly for samples which have a native oxide layer present between the In0.53Ga0.47As surface and the high-k oxide, suggesting that the charge trapping responsible for the C-V hysteresis is taking place primarily in the interfacial oxide transition layer between the In0.53Ga0.47As and the ALD deposited oxide. Analysis of samples with a range of oxide thickness values also demonstrates that the magnitude of the C-V hysteresis window increases linearly with the increasing oxide thickness, and the corresponding trapped charge density is not a function of the oxide thickness, providing further evidence that the charge trapping is predominantly localised as a line charge and taking place primarily in the interfacial oxide transition layer located between the In0.53Ga0.47As and the high-k oxide.
High dielectric constant hafnium oxide films were formed by electron beam (e-beam) evaporation on HF last terminated silicon (100) wafers. We report on the influence of low energy argon plasma and oxygen flow rate on the electrical, chemical, and structural properties of metal-insulator-silicon structures incorporating these e-beam deposited films. The use of the film-densifying low energy argon plasma during the deposition results in an increase in the equivalent oxide thickness (EOT) values. We employ high resolution transmission electron microscopy (HRTEM), x-ray photoelectron spectroscopy (XPS), and medium energy ion scattering experiments to investigate and understand the mechanisms leading to the EOT increase. We demonstrate very good agreement between the interfacial silicon oxide thicknesses derived independently from XPS and HRTEM measurements. We find that the e-beam evaporation technique enabled us to control the interfacial layer thickness down to . Very low leakage current density is measured at flatband voltage into accumulation for an estimated EOT of . Based on a combined HRTEM and capacitance-voltage analysis, employing a quantum-mechanical fitting procedure, we determine the dielectric constant of films, and associated interfacial layers, formed under various processing conditions. The values are found to be 21.2 for and 6.3 for the thinnest interfacial layer. The cross-wafer variations in the physical and electrical properties of the films are presented.