An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

In this paper, a D-band monolithic microwave integrated circuit low noise amplifier (LNA) is designed by using 0.5 μm InP high electron mobility transistor (HEMT) technology. The circuit is mainly composed of five-stage of common-source amplification structure, and resistance and capacitance are connected in series to form a feedback network, which can improve the stability of the circuit. The series resistance and parallel grounding capacitance on the DC bias circuit constitute a low-pass structure, which is to absorb the gain of the circuit at low frequency, prevent the circuit from self-oscillation. In the 120-150GHz frequency range, the simulated gain is above 18.5 dB, and the noise figure is lower than 4.5dB. The area of this chip is 1.12×0.62mm ² , and the power consumption of the whole circuit is 47mW.

A compact broadband monolithic sub-harmonic mixer is presented in a 70 nm GaAs Technology for millimeter wave wireless communication application. The proposed mixer adopts a novel multi-line coupler structure; where the two-sided coupling energy of radio frequency (RF) and local oscillation (LO) signals are both collected and efficiently feed to anti-parallel diode pair (APDP) topology; resulting in broadband performance and compact chip size. As a comparison in the same circuit configuration; the five-line coupler can expand the bandwidth of the existing three-line coupler by 85% and reduce the area by 39.5% when the central frequency is 127 GHz. The measured conversion gain is −16.2 dB to −19.7 dB in a wide operation frequency band of 110–170 GHz. The whole chip size is 0.47 × 0.66 mm² including test pads. The proposed mixer exhibits good figure-of-merits for D-band down-converter applications

Multi-band millimeter-wave (mm-wave) circuits are crucial for achieving high speed, high efficiency, flexible networking, and reducing hardware costs in mm-wave communication. This tutorial overviews three main types for multi-band mm-wave circuits, including wideband, concurrent multi-band, and reconfigurable multi-band. The implementation methods of multi-band circuits are analyzed and compared in detail from the perspective of device and circuit topology. The tutorial systematically reviews typical multi-band mm-wave circuits, including low noise amplifiers (LNAs), power amplifiers (PAs), variable gain amplifiers (VGAs) and attenuators (ATTs), phase shifters (PSs), mixers, signal sources, and transceivers (TRXs). Finally, the future trends are also discussed.

In this paper two types of waveguide-to-microstrip E-plane probe transitions are designed and analyzed by using the advanced electromagnetic simulation software HFSS in the WR4 frequency range, the center frequency is 220GHz. The first structure has been realized on 50um thick quartz substrates with S11 below -22dB and S21 below 0.88dB over the entire frequency band, and simulation results for quartz substrates of 50um and 100um thickness are compared. The second structure has been realized on 50um thick gallium arsenide substrate, S11 less than -10dB, S21 less than 1.3dB. Finally, the simulation results of the two structures are compared.

Continuous variable attenuator with wide bandwidth has been designed and fabricated in a 65nm CMOS process. This π-type with three shunt FETs in one side demonstrates state-of-the art performance showing a minimum insertion loss of 0.13-2.48 dB and good matching across the whole band. The attenuator has a continuous controllability from DC-110GHz with an attenuation range more than 16 dB as voltage bias changed constantly varies from 0 to 1.2V. Measurements also show return loss is greater than -22dB from 10 to 110GHz. The chip size is 340×280um ² and the core area is 26×109um ² .