This paper presents a complete mathematical design of the main components of 2 kW, 54 direct current (DC)–DC converter stage, which can be used as the second stage of the two stages of alternating current (AC)–DC telecom power supply. In this paper, a simple inrush current controlling circuit to eliminate the high inrush current, which is generated due to high input capacitor at the input side of the DC–DC converter, is proposed, designed, and briefly discussed. The proposed circuit is very easy to implement in the lab using a single metal–oxide–semiconductor field-effect transistor (MOSFET) switch and some small passive elements. PSIM simulation has been used to test the power supply performance using the value of the designed components. Furthermore, the experimental setup of the designed power supply with inrush current control is built in the lab to show the practical performance of the designed power supply and to test the reliability of the proposed inrush current mitigation circuit to eliminate the high inrush current at initial power application to the power supply circuit. DC–DC power supply with phase shift zero voltage switching (ZVS) technique is chosen and designed due to its availability to achieve ZVS over the full load range at the primary side of the power supply, which reduces switching losses and offers high conversion efficiency. High power density DC–DC converter stage with smooth current startup operation, full load efficiency over 95%, and better voltage regulation is achieved in this work.

Power system disruptions can be categorized as issues with the quality of electricity brought on by voltage sags, lightning strikes, and other system-related interferences. The static transfer switch (STS) has recently emerged as the most important technology for electric power transmission, distribution, and control systems to manage power supply during power system disruption issues, particularly in cost-effectively supplying power to critical loads and sensitive loads without interruption. In this paper, for the switching between the two AC sources during the voltage disruptions issue with low transfer time, a smart static transfer switch (SSTS) based on a digital switching algorithm and Triac semiconductor switch is proposed and experimentally tested. A digital switching algorithm based on online AC voltage sensing and zero-crossing detection is proposed and implemented inside a DSP MCU. The printed circuit board (PCB) of the proposed SSTS is designed and manufactured for the experimental performance investigation with different AC input voltage conditions. A comparative study based on the advantages and disadvantages of the proposed SSTS system with the previous works is also presented. A smart static transfer switch with a transition time of less than one cycle and a digital protection technique during fault conditions is obtained in this work.

During the last few decades, insulated-gate bipolar transistor (IGBT) power modules have evolved as reliable and useful electronic parts due to the increasing relevance of power inverters in power infrastructure, reliability enhancement, and long-life operation. Excessive temperature stresses caused by excessive power losses frequently cause high-power-density IGBT modules to fail. As a result, module temperature monitoring techniques are critical in designing and selecting IGBT modules for high-power-density applications to guarantee that temperature stresses in the various module components remain within the rated values. In this paper, a module’s different losses were estimated, a heating pipe system for the thermal power cycling technique was proposed, and finite element method (FEM) thermal modeling and module temperature measurement were performed using ANSYS Icepak software version 2022 R1 to determine whether the IGBT module’s temperature rise was within acceptable bounds. To test the proposed technique, a proposed design structure of the practical railway application with a 3.3 MW traction inverter is introduced using commercialized IGBT modules from Semikron company with maximum temperature of about 150 °C. the FEM analysis results showed that the maximum junction temperature is about 109 °C which is in acceptable ranges, confirming the appropriate selection of the employed IGBT module for the target application.

The spread of the 5G technology in the telecom power applications increased the need to supply high power density with higher efficiency and higher power factor. Thus, in this paper, the performance of the different power factor correction ( PFC ) topologies implemented to work with high power density telecom power applications are investigated. Two topologies, namely the conventional and the bridge interleaved continues-current-conduction mode (CCM) PFC boost converters are designed. Selection methodology of the switching elements, the manufacturing of the boost inductors, and the optimal design for the voltage and current control circuits based on the proposed small signal stability modeling are presented. The printed circuit board (PCB) for the two different PFC topologies with a power rating of 2 kW were designed. PSIM simulation and the experiments are used to show the supply current total harmonic distortions (THD), voltage ripples, power efficiency, and the power factor for the different topologies with different loading conditions.

This paper presents an optimal design for the inner current-control loop of the continuous current conduction mode (CCM) power factor correction (PFC) stage, which can be used as the front stage of the two-stage AC/DC telecom power supply. The conventional single-phase CCM-PFC boost converter is implemented with proportional–integral (PI) controllers in both the voltage and current-control loops to regulate the output DC voltage to the specified value and to ensure the input current follows the input voltage, which offers a converter with a high-power factor (PF) and low current total harmonic distortion (THD). However, due to the slow dynamic response of the PI controller at the zero-crossing point of the input supply current, the input current cannot fully follow the input voltage, which leads to high THD. In this paper, we investigate a digitally controlled PFC converter with an optimally designed inner current-control loop using a doubly-fed control loops integral-proportional (IP) controller to reduce the THD and to offer an input current with a unity PF. For the economic design of a digitally controlled PFC converter, two isolated AC and DC voltage sensors are designed for interfacing with the microcontroller unit (MCU). PSIM software as well as experimental prototype was used to test the converter performance using the proposed designed current controllers and isolated voltage sensors. We achieved a high-power-density, digitally controlled, telecom PFC stage with a power factor more than 99% and THD of about 5.50%.

This paper proposes a novel, degradation-sensitive, adaptive SST controller for cascode GaN-FETs. Unlike in traditional transformers, a semiconductor switch’s degradation and failure can compromise its robustness and integrity. It is vital to continuously monitor a switch’s health condition to adapt it to mission-critical applications. The current state-of-the-art degradation monitoring methods for power electronics systems are computationally intensive, have limited capacity to accurately identify the severity of degradation, and can be challenging to implement in real time. These methods primarily focus on conducting accelerated life testing (ALT) of individual switches and are not typically implemented for online monitoring. The proposed controller uses accelerated life testing (ALT)-based switch degradation mapping for degradation severity assessment. This controller intelligently derates the SST to (1) ensure robust operation over the SST’s lifetime and (2) achieve the optimal degradation-sensitive function. Additionally, a fast behavioral switch loss model for cascode GaN-FETs is used. This proposed fast model estimates the loss accurately without proprietary switch parasitic information. Finally, the proposed method is experimentally validated using a 5 kW cascode GaN-FET-based SST platform.