Ayan Mallik

Dr. Ayan Mallik

Power Electronics and Control Engineering Laboratory, The Polytechnic School (TPS), Arizona State University, Tempe, AZ 85281, USA

Research Focus & Metrics

Academic Career Length

10Years (2017-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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13 November 2017 in IEEE Transactions on Industry Applications
Verified
Journal Article
Open access
Shenli ZouShenli Zou
Shenli Zou
JLJiangheng Lu
Jiangheng Lu
Ayan MallikAyan Mallik
Ayan Mallik
AKAlireza Khaligh
Alireza Khaligh
This paper presents an innovative technique for synchronous rectification in the bidirectional CLLC converter with the integrated transformer for plug-in electric vehicle (EV) applications. To improve the efficiency and power density, the integrated transformer is introduced and simulated using Finite Element Analysis (FEA) method. In addition, synchronous rectification method is implemented by controlling the turn-on and turn-off timings based on the phase difference between resonant currents of primary and secondary sides. Furthermore, a simplified closed loop design is discussed and implemented on a digital signal processor (TMS320F28335). The effectiveness of the control loop is verified through the experimental results. A 3.3kW proof-of-concept prototype is built with power density of 1kW/L, a gravimetric power density of 0.9kW/kg and peak efficiency of 97.5%.

14 November 2018 in IEEE Transactions on Vehicular Technology
Verified
Journal Article
Closed access
PHPeiwen He
Peiwen He
Ayan MallikAyan Mallik
Ayan Mallik
ASArun Sankar
Arun Sankar
AKAlireza Khaligh
Alireza Khaligh
In this paper, a bidirectional CLLC converter operating at MHz-level switching frequency is proposed to achieve high power density and high efficiency. An optimized stacked printed circuit board (PCB) winding based planar transformer with adjustable leakage inductance is modeled and designed for the proposed converter. It is enabled using Gallium nitride (GaN) devices to achieve fast switching with low switching losses. A detailed power loss model is established for the efficient thermal design of the converter. A proof-of-concept hardware of 3.3 kW, 400-450 VDC input, 250-420 VDC output CLLC converter with 1 MHz operating frequency is built and tested over a wide range of loading conditions. The power density of the system is 9.22 W/cm $^3$ (151.1 W/in $^3$ ) and the peak efficiency achieves over 97%.

19 October 2018 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
ASArun Sankar
Arun Sankar
Ayan MallikAyan Mallik
Ayan Mallik
AKAlireza Khaligh
Alireza Khaligh
Synchronous rectification (SR) is one of the well-known methods to reduce the conduction losses by replacing the power diodes. The control of SR requires the phase information of the device current. In this paper, a novel extended harmonics approximation modeling approach is introduced for CLLC resonant converters to estimate the phase of its secondary side current accurately. Conventionally, the first harmonic approximation (FHA) is used to model any resonant converter; however, FHA works more accurately near the resonant frequency operation. But in case of a set of unmatched LC tank parameters in the primary and secondary side of a CLLC converter, there is no uniquely defined resonant frequency, which reduces the accuracy of the FHA model. Unlike FHA-based approach, our proposed modeling considers the effects of other odd order harmonics present in the square wave voltage waveform towards determining the zero-crossing instant or phase information of the resonant currents. The proposed concept is verified through experimental results obtained at 3.3-kW load condition, and the converter efficiency is improved by 1.8% with the proposed phase tracking technique, compared to FHA modeling approach.

16 December 2020 in IEEE Access
Verified
Journal Article
Open access
ACAshwin Chandwani
Ashwin Chandwani
SDSaikat Dey
Saikat Dey
Ayan MallikAyan Mallik
Ayan Mallik
In this paper, the impacts of various data integrity attacks on the power electronic hardware present in an EV charger are comprehensively analyzed in order to provide necessary recommendations to defend against cyberattacks on electric vehicles and their onboard charging (OBC) systems. The adverse scenarios arising due to cyberattacks are carefully reviewed in this study, which includes (a) interfering with the main charger controller (FPGA) logic and its data, (b) establishing fake communication between the charging controller and other electronic control units (ECUs) connected over same controller area network (CAN) bus, and (c) interfering with the battery management system functionalities. A 6.6kW interleaved totem-pole PFC front-end followed by a high frequency DC-DC converter is used as our OBC representative system in this analysis. Possibilities and ways of potential cyberattacks on this model are investigated in detail. Effort is made towards providing software as well as hardware design-level protection mechanisms to mitigate the malicious effects of such cyberattacks on the OBC hardware. This system is simulated in MATLAB/Simulink to verify the fault occurrences under various data integrity attacks as well as to validate the effectiveness of our proposed countermeasure approaches. Quantitative analyses of the obtained results clearly demonstrate that if adequate precautionary measures are properly taken while designing the charging architecture (e.g., implementing intelligence to the main controller), any electrical hazard or deterioration of health of the components can be avoided to the maximum extent under the circumstances of a malicious cyberattack.

7 January 2022 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
SDSaikat Dey
Saikat Dey
Ayan MallikAyan Mallik
Ayan Mallik
This article presents the design, development, and optimization of pulsewidth modulation (PWM) scheme of an isolated bidirectional triple-active-bridge (TAB) dc–dc converter composed of three full-bridge modules and a high-frequency planar transformer. This article aims at improving the efficiency of the TAB converter by means of conduction loss minimization. The approach utilizes multiple control variables as degrees of freedom for the converter modulation. The optimization is based on the minimization of the true rms current, formulated using generalized harmonic approximation technique. The approach constitutes of two steps: the modulation pattern with least algorithmic complexity for efficiency maximization is first found depending on the operating load and gain condition, and, subsequently, the optimum control variables are calculated using the gradient descent algorithm applied on the identified modulation pattern. An 800-W TAB converter proof-of-concept is built to verify all theoretical considerations and model-oriented analysis. While the converter has an input dc bus voltage of 160 V, the two output ports of the converter can deliver 400 W each at voltage levels of 110–130 V and 18–27 V, respectively. With the implementation of the proposed optimal phase-duty control, the experimental results show a nonunity gain light load efficiency increment up to 6.1% compared with the conventional modulation technique.

18 June 2018 in IEEE Transactions on Vehicular Technology
Verified
Journal Article
Closed access
Ayan MallikAyan Mallik
Ayan Mallik
JLJiangheng Lu
Jiangheng Lu
AKAlireza Khaligh
Alireza Khaligh
In this paper, a comprehensive sliding mode control (SMC) loop design for single-phase interleaved totem pole (ILTP) power factor correction (PFC) converters for electric vehicle (EV) onboard charger applications is proposed. The major objectives of the proposed SMC are to improve the converter dynamics, ensure a tight output voltage regulation under fast load fluctuations, and maintain a unity power factor. The sliding mode coefficients are selected to ensure both small signal and large signal stability for the robustness of the converter in wide operating conditions. As verification to the proof-of-concept, a hardware prototype of a single-phase ILTP PFC is developed and tested to validate the effectiveness of loop design by the load transient tests. The steady state results exhibit a power factor > 0.995 and total harmonic distortion (THD) < 3% at 800W load power. At a 25% step-change in load power, SMC achieves 80 ms settling time, which is approximately 200 ms faster than the conventional PI control.