This article describes a 4 x 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain-BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195 mW. The following DFE-FFE-based digital equalizer is capable of compensating 36-dB loss achieving a BER of 2e-5. Furthermore, TDC and ISI filter-based low-latency timing recovery meet jitter tolerance specs over a wide range of data rates from 10 to 112 Gb/s, including 28-Gb/s NRZ. The overall receiver consumes 338 mW with 3.18-pJ/bit energy efficiency.

This article presents a multiprotocol DSP-DAC-based SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)-based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The LC PLL generates 10.25-14.5 GHz but distributes a divided version of the clock between 2.25 and 3.625 GHz with less than 140-fs integrated jitter. The local ring PLL multiplies the clock to 28 GHz but keeps the jitter less than 180 fs thanks to wide loop bandwidth. The transmitter is implemented in 7-nm FinFET consuming 175 mW with 1.56-pJ/bit efficiency.

This paper aims to investigate a high-power and low-cost monopulse transmitter circuit for underground and underwater sensing and imaging. The transmitter utilizes two Marx transistor-based pulse generators, a balun, and a Vivaldi antenna. A simple output network, including an inductor and Schottky diode, is employed to compensate for the ringing level and distortion and improve the pulse width. The ringing level of the developed circuit is around 6 percent. The output is a Gaussian pulse with pulse width and amplitude of 481 ps and 50 V, respectively. In order to have a high amplitude monopulse, an exact replica of this network in parallel is exploited. The outputs of the parallel circuits are subtracted through the balun to have a dc -free monopulse with amplitude and pulse width of 26 V and 483 ps, respectively. The monopulse is radiated by a Vivaldi antenna toward a buried object. The image of the target is generated using the time-domain global back projection (TD-GBP) method. Three imaging experiments are conducted to verify the functionality of the designed sensor system. The reconstructed images and the reference images are shown high structural similarity indexes of 98.6%, 95.4%, and 97.6%.

A low-power channel-adaptive 28 Gb/s PAM-4 receiver is presented utilizing a predictive analog-to-digital converter (ADC), a successive-approximation-register (SAR) time-to-digital converter (TDC), and a feed-forward equalizer (FFE) in the digital domain. The variable-resolution flash ADC takes advantage of the channel inter-symbol interference (ISI) and can achieve 5.5 bits resolution utilizing only 16 comparators. By reusing the comparators, the ADC can provide a programmable resolution from 2 to 5.5 bits consuming 40 to 90 mW, respectively. The SAR-TDC generates 5 bits timing information that includes 2 bits ISI and 3 bits timing error to achieve a low-latency and low-jitter timing recovery. Subsequently, a three-to-eight programmable tap FFE is used to equalize up to 30-dB loss achieving bit error rate lower than 10⁻⁸. FFE is implemented in a field-programmable gate array, and the first three taps are realized in a look-up table (LUT). An offline higher resolution ADC is used to generate the pre-computed values for the LUT. Measured power consumption is 130 mW (excluding digital signal processing) from a 1.2-V power supply with active chip area of 0.2025 mm$²$ in 65-nm technology. Due to programmability on the both ADC resolution and the number of FFE taps according to the channel loss, the receiver enables energy efficiency according to loss compensation.

This article explores different modulation and signaling techniques with the goal to achieve 224-Gb/s link speed through electrical signaling. Focus of this work spans from interconnects to transceiver architecture from system and signaling point of view. In addition to traditional multilevel signaling pulse amplitude modulation-4 (PAM-4 and PAM-8), this work also compares simultaneous bidirectional signaling and multiwire encoding techniques as potential solutions beyond 224-Gb/s link. These signaling options are compared both from performance and implementation complexity point of view with possible improvements required to further extend the speed and reach of electrical signaling.

This paper describes a low-power, low-latency, $7–10\mathrm{Gb}/\mathrm{s}$ burst-mode DC-coupled receiver for photonic switch networks. The receiver includes a transimpedance amplifier (TIA) followed by a three-stage differential amplifier. For burst-mode operation, DC and timing recovery loops work concurrently in the proposed architecture to achieve 5.8 ns lock time. The DC recovery loop employs a successive approximation algorithm to recover signal-dependent offset that takes only six cycles of C8 (1/8th of data rate) clock. The timing recovery uses a quarter-rate injection scheme that is immune to duty cycle distortion. The recovered clock jitter is 10 ps p-p for $10\mathrm{Gb}/\mathrm{s}$ operation. The receiver consumes only 33 mW while operating at $10\mathrm{Gb}/\mathrm{s}$, and less than 2 mW (leakage power and bias circuit) during idle time. The completely inductor-less receiver occupies a $465\mathrm{\mu m}\times 265\mathrm{\mu m}$ area in 0.13 μm technology.