Recently, the application of machine learning on embedded systems has drawn interest in both the research community and industry because embedded systems located at the edge can produce a faster response and reduce network load. However, software implementation of neural networks on Central Processing Units (CPUs) is considered infeasible in embedded systems due to limited power supply. To accelerate AI processing, the many-core Graphics Processing Unit (GPU) has been a preferred device to the CPU. However, its energy efficiency is not still considered to be good enough for embedded systems. Among other approaches for machine learning on embedded systems, neuromorphic processing chips are expected to be less power-consuming and overcome the memory bottleneck. In this work, we implemented a pedestrian image detection system on an embedded device using a commercially available neuromorphic chip, NM500, which is based on NeuroMem technology. The NM500 processing time and the power consumption were measured as the number of chips was increased from one to seven, and they were compared to those of a multicore CPU system and a GPU-accelerated embedded system. The results show that NM500 is more efficient in terms of energy required to process data for both learning and classification than the GPU-accelerated system or the multicore CPU system. Additionally, limits and possible improvement of the current NM500 are identified based on the experimental results.

The rapid expansion of IoT devices poses new challenges for AI-driven services, particularly in terms of energy consumption. Although cloud-based AI processing has been the dominant approach, its high energy consumption calls for more energy-efficient alternatives. Edge computing offers an approach for reducing both latency and energy consumption. In this paper, we propose a methodology for estimating the power consumption of AI accelerators on an embedded edge device. Through experimental evaluations involving GPU- and Edge TPU-based platforms, the proposed method demonstrated estimation errors below 8%. The estimation errors were partly due to unaccounted power consumption from main memory and storage access. The proposed approach provides a foundation for more reliable energy management in AI-powered edge computing systems.

As Programmable Logic Controllers (PLCs) are increasingly connected and integrated into the industrial Internet of things, cybersecurity threats to PLCs are also increasing. Adversaries can perform a denial of service (DoS) attack based on the transmission of a large number of network packets, and a control-logic injection attack through sophisticated packet transmission. We propose an approach to detecting and defending against attacks that exploit security vulnerabilities in a PLC system. In order to protect against indiscriminate packet transmission attacks that exploit uncontrolled resource consumption vulnerabilities, an abnormal temporal behavior detection method is proposed that monitors the CPU usage of tasks. If a temporal anomaly is detected, the proposed approach tries to detect control-flow anomalies by examining the sequences of function calls, then detects stack-based buffer overflow attacks. The proposed method is implemented in a water tank control system for evaluation purposes. The experimental results show that the proposed method can improve the security of the system by detecting anomalies in temporal behavior with little system overhead.

Mobile devices should be designed to meet two contradictory goals: providing the performance desired by users while minimizing the energy consumption to meet the users' expectation of the battery run-time. The heterogeneous multicore architecture has been introduced to mobile world for higher energy-efficiency and performance. It is possible, however, only when the operating system assigns the appropriate core for an application to take full advantage of the heterogeneity. This article addresses the problem of the core selection for mobile devices with a heterogeneous multicore processor. It is shown that core switching for less energy consumption must consider both core frequency and utilization at the same time.