Stability of negative bias temperature stress (NBTS) of nitrogen doped amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) is investigated. Undoped a-IGZO TFT stressed at 333 K exhibit a larger negative ΔV_TH (−3.21 V) with an unpredictable sub-threshold swing (SS) of hump shaped transfer curve due to the creation of meta-stable traps. Defects related hump formation has disappeared with small ΔV_TH (−1.13 V) and ΔSS (0.018 V/dec) in nitrogen doped a-IGZO TFT. It is observed that nitrogen doping enhances device stability by well controlled oxygen vacancy and trap sites in channel and channel/dielectric interface.

An experiential aspect regarding the improvement of retention characteristics of InSnZnO (ITZO) thin-film transistor-based nonvolatile memory (TFT-NVM) devices with a hydrogen peroxide H ₂ O ₂ treated Aluminum oxide (Al ₂ O ₃ ) tunneling layer is reported. A better performance in retention of ~92% (after ten years), a smaller subthreshold swing of 96 mV/decade, and a higher field effect mobility of 31.08 cm ² /V·s were obtained in H ₂ O ₂ treated TFT-NVM devices compared with untreated one. Furthermore, employing the H ₂ O ₂ -treatment in the Al ₂ O ₃ layer provided oxygen-rich (O/Al ratio = 1.45) and OH-residuals free Al ₂ O ₃ , which effectively minimized the interface states (1.34 × 1011 cm ^-2 eV ^-1 ) between the ITZO/(Al ₂ O ₃ /SiOx/SiO ₂ ) stack through strong oxidation. These results suggest that high-quality Al ₂ O ₃ dielectric layer can be obtained through cost-effective H ₂ O ₂ oxidation techniques for TFT-NVM devices.

In this work, a simple method to form small random pyramid texturing (0.5–2 μm size) is proposed to enhance the surface passivation of commercial p-type Cz-Si wafers. Small pyramid texturing was generated with chemical nano-masking for anisotropic etching. The surface recombination velocity obtained after the passivation of the thermal oxide layer reduced from 65 and 10 cm s⁻¹ for the large pyramids (10–15 μm size) and small pyramid (0.5–2 μm) texturing respectively. The solar cell fabricated with large pyramid texturing resulted in an efficiency of 17.82% with a current density (J_SC) of 36.91 mA cm⁻², an open circuit voltage (V_OC) of 620 mV whereas small pyramid texturing resulted in an efficiency of 18.5% with J_SC of 37.6 mA cm⁻² and V_OC of 628 mV. The low surface recombination velocity increases the V_OC by 8 mV. The small pyramid textured wafers are found to enhance the quantum efficiency performance in both short and long wavelength regions.

Effect of short-channel induced instabilities in InSnZnO-based thin-film transistors (TFTs) caused by combination of the drain induced barrier lowering (DIBL) and parasitic resistance is reported. As the active channel length decreased below a critical value of around 8 μm, the draincurrent (2.81 μA) are abruptly increased and N-shaped behavior of the transconductance are observed due to the formation of additional current path in the channel. The magnitude of subgap density of states is also depended on the channel size. The higher value of parasitic resistance RSD (~42 kg) and DIBL coefficient (76.8 mV/V) in short-channel ITZO TFT devices are also discussed.