This study explores the application of Generative Adversarial Networks (GANs) for generating wafer-level Wafer Acceptance Test (WAT) and Chip Probe (CP) test data in chip manufacturing processes, with a focus on Design-Technology Co-Optimization (DTCO). The generated virtual silicon data encompasses essential performance characteristics, physical electrical properties, wafer-level process parameter distributions, as well as implicit information about wafer-level uniformity and defects. This information represents non-random features on wafers, such as similar distorted wafer surfaces observed in lots produced from various batches. This innovative approach overcomes data acquisition barriers, efficiently compresses large datasets while ensuring data confidentiality, and holds immense potential for the development of advanced Electronic Design Automation (EDA) tools, enabling the synergistic optimization of manufacturing processes and chip design flow.

As the gap between processor and memory speeds continues to widen, methods for measuring memory system designs before they are implemented in hardware are becoming increasingly important. The performance of the bus protocol maintaining the coherence of the same data in all caches for the shared-memory multiprocessors can be measured in advance by many analytical methods, the inevitable use of a simplified assumption to analyze a computer system with increasing complexity restrictions the predetermined conditions of the analytical results. The study introduces the development, implementation and future work for a trace-driven memory simulator for shared-memory multiprocessors. The simulator can measure the performance for different multiprocessors architectures under real operating systems and applications as a reference for the decision on the design or modification of the system, with the aim of increasing production efficiency and save R&D expenses.