Many embedded systems are indeed software-based control systems , that is, control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on formal model-based design approaches for automatic synthesis of embedded systems control software. We present an algorithm, along with a tool QKS implementing it, that from a formal model (as a discrete-time linear hybrid system ) of the controlled system ( plant ), implementation specifications (that is, number of bits in the Analog-to-Digital , AD, conversion) and system-level formal specifications (that is, safety and liveness requirements for the closed loop system ) returns correct-by-construction control software that has a Worst-Case Execution Time (WCET) linear in the number of AD bits and meets the given specifications. We show feasibility of our approach by presenting experimental results on using it to synthesize control software for a buck DC-DC converter, a widely used mixed-mode analog circuit, and for the inverted pendulum.

In management tasks for modern electricity networks the stakeholders face typically two conflicting objectives: maximization of income (increasing demand) and reduction of demand peaks (reducing costs). To improve management of electricity distribution networks, an integrated service-based methodology is presented in this paper. Namely, the proposed approach: i) computes the operational constraints in order to improve utilization of the whole network; ii) enforces those constraints by focusing on each network substation separately; iii) verifies that probability of violating those constraints in nonnominal cases is fairly low. The feasibility of the approach has been tested tested by using a realistic scenario taken from an existing medium voltage Danish distribution network. In such scenario, the proposed method improves the network utilization and offers economic benefits for all the principal participants, i.e. DSOs, retailers and end users.

The goal of System Level Formal Verification (SLFV) is to show system correctness notwithstanding uncontrollable events (such as: faults, variation in system parameters, external inputs, etc). Hardware In the Loop Simulation (HILS) based SLFV attains such a goal by considering exhaustively all relevant simulation scenarios. We present a distributed multi-core algorithm for HILS-based SLFV. Our experimental results on the Fuel Control System example in the Simulink distribution show that by using 64 machines with an 8 core processor each we can complete the SLFV activity in about 27 hours whereas a sequential approach would require more than 200 days. To the best of our knowledge this is the first time that a distributed multi-core algorithm for HILS-based SLFV is presented.