Automation has been responsible for the most important breakthroughs in testing, and it is now a fundamental element of the electronics world. Unfortunately, its progress is now limited by several legacy solutions that are implicitly, and sometimes unknowingly, accepted. The duality Generation/Application of patterns is at the very heart of today’s testing ecosystem, but it is being challenged by the very evolutions it,fostered. The IEEE 1687 standard is symptomatic to this: it proposes hardware and software solutions to boost hierarchical and instrument-based testing, but is full application brings the current Automated Test Flow close to breaking point. It is a typical scaling issue: everything seems fine for small-scale systems in the short term, but problems arises when looking at long-term. In this paper, we focus on the long-term vision to uncover and explain these limiting elements. We then propose a new flow that overcomes them, unleashes the full potential of new approaches, and fosters evolution.

The new IEEE 1687 standard provides important novelties, such as dynamic topology and access to deeply embedded instruments. Unfortunately, traditional tool flows are not able to fully address this potential. In this paper we will point out the shortcomings of legacy approaches while proposing a new, backward compatible flow optimized for functional usage of instruments.

Functional Safety standards like ISO 26262 require a detailed analysis of the dependability of components subjected to perturbations. Radiation testing or even much more abstract RTL fault injection campaigns are costly and complex to set up especially for SoCs and Cyber Physical Systems (CPSs) comprising intertwined hardware and software. Moreover, some approaches are only applicable at the very end of the development cycle, making potential iterations difficult when market pressure and cost reduction are paramount. In this tutorial, we present a summary of classical state-of-the-art approaches, then alternative approaches for the dependability analysis that can give an early yet accurate estimation of the safety or security characteristics of HW-SW systems. Designers can rely on these tools to identify issues in their design to be addressed by protection mechanisms, ensuring that system dependability constraints are met with limited risk when subjected later to usual fault injections and to e.g., radiation testing or laser attacks for certification.

We present a hardened RTL processor core based on Leon2. Modifications are done at RT-level to achieve high configurability in an early stage of the development process. The main parts of the processor core can be protected against Single Event Upsets and Single Event Transients. Results and tradeoffs are presented and discussed

This article highlights the challenge of making dynamic IJTAG operational. While the PDL allows flexibility, it generates problems for the back-end, which is how IJTAG operations are combined and executed.

New semiconductor technologies for advanced applications are more prone to defects and imperfections related, among several different causes, to the manufacturing process, aging and cross-talks. These phenomena negatively affect the circuit’s timing and can be effectively modeled by means of the path delay fault (PDF) model. While path delay testing is currently supported by commercial Automatic Test Pattern Generation tools for scan designs, functional testing covering PDFs is not widely adopted, mainly because of the high cost for test generation. On the other side, functional test is already widely adopted for in-field test of stuck-at faults, which is often performed resorting to the execution of suitable test programs (Self Test Libraries, or STLs). This approach is attractive, since it can be performed at-speed with limited time constraints and high flexibility, making it a suitable in-field test solutions. Previous work assessed the feasibility and validity of functional approaches based on test programs targeting PDFs. In this work, we present the first systematic method for the development of very high fault coverage test programs for PDFs, which largely outperform test programs written for other fault models. Moreover, the proposed method allows the identification of functionally untestable faults. The effectiveness of the proposed approach was proven on an open-source RISC-V processor core, where 100% coverage of the functionally testable longest paths was achieved, compared with an initial coverage of 0.52% achieved with test programs targeting stuck-at faults. Results demonstrate that shorter paths are also effectively covered.