The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

LED is an ultra-lightweight block cipher targeting resource-constrained devices. The current hardware architectures of this cipher utilize large logic area, operate in low frequencies and have low throughput. To improve the trade-offs between area utilization and performance, an iterative round-based architecture of LED block cipher is implemented in this paper. LED algorithm is available in 64-bit and 128-bit key sizes. In this paper, the focus is on the 64-bit key with 64-bit block size. This algorithm is implemented on various Field Programmable Gate Array (FPGA) devices. The design is verified on several Altera and Xilinx devices using Altera Quartus II, ModelSim and Xilinx ISE simulators. Both low-cost and high-end FPGA devices were targeted. Tradeoffs between area and performance were considered, with the optimization for performance. The throughput and maximum operating frequency are benchmarked with the existing literature and better performance is achieved. The results show large improvements in maximum operating frequency and throughput as well as reduction in area utilization compared to recent designs of round-based LED block cipher.

IoT devices and embedded systems are deployed in critical environments, emphasizing attributes like power efficiency and computational capabilities. However, these constraints stress the paramount importance of device security, stimulating the exploration of lightweight cryptographic mechanisms. This study introduces a lightweight architecture for authenticated encryption tailored to these requirements. The architecture combines the lightweight encryption of the LED block cipher with the authentication of the PHOTON hash function. Leveraging shared internal operations, the integration of these bases optimizes area–performance tradeoffs, resulting in reduced power consumption and a reduced logic footprint. The architecture is synthesized and simulated using Verilog HDL, Quartus II, and ModelSim, and implemented on Cyclone FPGA devices. The results demonstrate a substantial 14% reduction in the logic area and up to a 46.04% decrease in power consumption in contrast to the individual designs of LED and PHOTON. This work highlights the potential for using efficient cryptographic solutions in resource-constrained environments.