In a wireless power transfer (WPT) system via the magnetic resonant coupling, one of the most challenging design issues is to maintain a reasonable level of power transfer efficiency (PTE), even when the distance between the transmitter and the receiver changes. When the distance varies, the PTE drastically decreases due to the impedance mismatch between the resonator of the transmitter and that of the receiver. This paper presents a novel serial/parallel capacitor matrix in the transmitter, where the impedance can be automatically reconfigured to track the optimum impedance-matching point in the case of varying distances. The dynamic WPT matching system is enabled by changing the combination of serial and parallel capacitors in the capacitor matrix. An interesting observation in the proposed capacitor matrix is that the resonant frequency is not shifted, even with capacitor-matrix tuning. In order to quickly find the best capacitor combination that achieves maximum power transfer, a window-prediction-based search algorithm is also presented in this paper. The proposed resonance WPT system is implemented using a resonant frequency of 13.56 MHz, and the experimental results with 1W power transfer show that the transfer efficiency increases up to 88 % when the distance changes from 0 to 1.2 m.

With an increasing demand for artificial intelligence, the emulation of the human brain in neuromorphic computing has led to an extraordinary result in not only simulating synaptic dynamics but also reducing complex circuitry systems and algorithms. In this work, an artificial electronic synaptic device based on a synthesized MoS₂ memristor array (4 × 4) is demonstrated; the device can emulate synaptic behavior with the simulation of deep neural network (DNN) learning. MoS₂ film is directly synthesized onto a patterned bottom electrode (Pt) with high crystallinity using sputtering and CVD. The proposed MoS₂ memristor exhibits excellent memory operations in terms of endurance (up to 500 sweep cycles) and retention (~ 10⁴) with a highly uniform memory performance of crossbar array (4 × 4) up to 16 memristors on a scalable level. Next, the proposed MoS₂ memristor is utilized as a synaptic device that demonstrates close linear and clear synaptic functions in terms of potentiation and depression. When providing consecutive multilevel pulses with a defined time width, long-term and short-term memory dynamics are obtained. In addition, an emulation of the artificial neural network of the presented synaptic device showed 98.55% recognition accuracy, which is 1% less than that of software-based neural network emulations. Thus, this work provides an enormous step toward a neural network with a high recognition accuracy rate.

This paper presents ultrathin and highly sensitive input/output devices consisting of a capacitive touch sensor (Cap-TSP) integrated on thin-film-encapsulated active-matrix organic light-emitting diodes (OLEDs). The optimal structure of the electrically noise-free capacitive touch sensor, which is assembled on a thin-film-encapsulated active-matrix OLED (AMOLED) display, is obtained by investigating the internal electrical field distribution and capacitance change based on the Q3D Extractor model. Electrostatic simulations have verified malfunction-free electrical signals for 4-in diagonal-sized capacitive touch sensors on AMOLEDs possessing a 100-μm-thick optically clear adhesive (OCA, ε r = 1.4) layer. The prototype OLED platform using the capacitive touch sensors exhibits an overall thickness of 1.2 mm, which is the lowest thickness for commercially available OLED platforms.

This paper presents a dynamic bit-width adaptation scheme for applications using discrete cosine transform (DCT). The technique can efficiently trade off image quality and computation energy. Based on sensitivity differences of 64 DCT coefficients, separate operand bit-widths are used for different frequency components to reduce computation energy. To select the appropriate operand bit-widths that achieve significant reduction of power consumption with minimum image quality degradation, we also propose a bit-width selection algorithm. The proposed variable bit precision DCT algorithm can be efficiently implemented using carry save adder trees. The reconfigurable DCT architecture can achieve power savings ranging from 36% to 75% compared to normal operation at the expense of minor image quality degradation.

In this paper, we present an energy-efficient architecture of the Canny edge detector for advanced mobile vision applications. Three key techniques for reducing computational complexity of the Canny edge detector are presented. First, by exploiting the rank characteristic of the convolution kernel of Gaussian smoothing and Sobel gradient filters, common computations are identified and shared in the image filter design to reduce the number of additions and multiplications. For the gradient magnitude/direction computation, only three directions of neighboring pixels are considered to reduce computation energy with minor degradation on conformance performance (CP). For the adaptive threshold selections, an interesting observation is that the mean values of gradient magnitudes show small variations depending on the classified block types. Thus, the threshold selection process can be simplified as multiplying the mean value of the local block with predecided constants. The proposed low complexity Canny edge detector has been implemented using both field-programmable gate arrays (FPGAs) and a 65-nm standard-cell library. The FPGA implementation with Xilinx Virtex-V (XC5VSX240T) shows that our edge detector achieves 48% of area and 73% of execution time savings over the conventional architecture without seriously sacrificing the detection performance. The proposed edge detector implemented with 65-nm standard-cell library can easily support real-time ultrahigh definition video data processing (50 frames/s) with the power consumption of 5.48 mW (108.84 μJ/frame).