A geomagnetic signal blind zone exists between the front and rear axle of high-chassis vehicle such as trucks and buses, which leads to multiple-detection problem in detecting those vehicles running at low speed on roads or error-detection problem in the case of the stopping position of the vehicle is not standard when waiting for the traffic light to change. In order to improve the detection accuracy of any type of vehicle running at any speed, a novel two-sensors data fusion vehicle detection method through combining received signal strength from radio stations with geomagnetism around vehicles is designed and verified in the paper. Experimental results show that the accuracy of our proposed method can reach 95.4% and traditional single magnetism-based detection method was only 83.4% in the detection of high-chassis vehicles.

With continued dimension scaling of the semiconductor devices, the parasitic parameters become increasingly obvious and it affects the device performance directly. The harmonic distortion is one of the key factors to limit the RF system bandwidth resource and channel capability. Therefore, it is crucial to precisely extract the nonlinear index of the device and system. High-precision harmonic distortion extraction on a device’s intrinsic characteristics could be beneficial not only to device modeling but also to circuit design. However, the harmonic distortion measurement is highly sensitive to the peripheral circuit and instrumentations, especially in high power stimulus; its repeatability and stability are also hard to control. This paper aims to contribute to the subject by extending the measurement methodology, combining isolation compensation with a dual trace phase tuning (DTPT) technique to obtain the optimal harmonic value. As shown by the experiment results, the optimized approach could achieve high measurements of both accuracy and stability. The proposed methodology is validated with measurement data and compared with conventional measurement architecture. The assessment results prove that the proposed methodology could improve 30.66% and 28.84% measurement accuracy both on second and third harmonics. Simultaneously, the proposed methodology decreases gauge repeatability and reproducibility (GRR) from 56.49% to 7.13%.

Modern system-on-a-chip SOC contains hierarchical cores that have multiple levels of design hierarchy. An efficient wrapper design for hierarchical cores is necessary to facilitate modular testing of SOC. In most of the prior work on wrapper design for embedded cores, all the cores are assumed to have a flattened hierarchy, it's not suitable for real-life SOCs. In this paper, a generic IEEE 1500-compliant wrapper architecture for hierarchical cores is presented. Unlike prior wrapper design methods that assume a single flattened mode for hierarchical core wrappers, the reconfigurable wrapper presented for hierarchical cores that can operate efficiently in all the test modes, and can be directly applicable to real-life SOCs and support for multiple levels of hierarchical cores. A procedure is also proposed to get the TAM BUS width reduced without increasing testing time. Experimental results have proved that the TAM BUS width can get reduced 45% at most compare to flattened mode.

With the increase in complexity of VLSI and the test cost of automatic test equipment (ATE), logic built-in self-test (BIST) has been widely applied. In order to reduce the test time of logic BIST, logic BIST with multiple scan chains has been proposed. However, the main shortcoming of logic BIST with multiple scan chains is low fault coverage (FC). A novel two-dimensional cellular automata (2-DCA), which is called two-dimensional restricted vertical neighbor cellular automata (2-DRVNCA), is proposed to resolve this problem. Using this 2-DRVNCA as pseudorandom test pattern generator (PRPG), high FC can be achieved. In the last, this PRPG is applied on some benchmark circuits of ISCAS'89, and average FC (82% ~ 89%) is obtained.