The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption.

This paper proposes a secure non-volatile main memory (NVMM) with a scratch pad memory (SPM) management compiler to reduce the number of bit flips in NVMM. The main idea is to categorize data to write-intensive and non write-intensive, and apply the CTR mode encryption for write intensive data and the ECB mode encryption for non write intensive data. The proposed scheme is secure against deterministic chosen plaintext physical attacks. Our experimental results show that the proposed dual encryption scheme reduces the number of flipped bits by 31.8% compared with ECB mode only encryption.

This paper proposes a fast memory access profiling tool called HMTool for multi-threaded applications. The proposed profiling tool extracts memory access patterns rapidly to optimize a multi-threaded application by allocating variables properly on a hybrid memory system with DRAM and non-volatile memory. To enhance the profiling performance, this paper proposes a static analysis and a caching technique for profiling. The proposed tool is implemented based on LLVM compiler framework. Experiment results show that the proposed profiling techniques improve the profiling performance by 5.1 times compared with an existing memory profiling tool.