A prototypical metal-organic framework (MOF), a 2D periodic porous structure based on the assembly of copper ions and benzene dicarboxylate (bdc) ligands (Cu(bdc)·xH₂O), was grown successfully as a thin film on interdigitated electrodes (IDEs). IDEs have been used for achieving planar CMOS-compatible low-cost capacitive sensing structures for the detection of humidity and volatile organic compounds (VOCs). Accordingly, the resultant IDEs coated with the Cu(bdc)·xH₂O thin film was evaluated, for the first time, as a capacitive sensor for gas sensing applications. A fully automated setup, using LabVIEW interfaces to experiment conduction and data acquisition, was developed in order to measure the associated gas sensing performance.

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33fJ/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3ppm/°C is achieved without the need for calibration.

The first reactance-less oscillator is introduced. By using a memristor, the oscillator can be fully implemented on-chip without the need for any capacitors or inductors, which results in an area-efficient fully integrated solution. The concept of operation of the proposed oscillator is explained and detailed mathematical analysis is introduced. Closed-form expressions for the oscillation frequency and oscillation conditions are derived. Finally, the derived equations are verified with circuit simulations showing excellent agreement.

Design productivity remains an important aspect in the analog integrated circuit design industry, as growing competition and shorter design cycles pressure the traditional flow that involves time-consuming manual iterations in a circuit simulator. This paper describes innovations within an alternative framework that uses precomputed look-up tables (LUTs) to enable fast and accurate evaluation of circuit sizing scenarios without a simulator in the loop. It lets the designer explore and understand the design space boundaries in a systematic setting, thus supporting informed decision making and architectural innovation that is difficult to attain with fully automated, black-box sizing tools. Our discussion begins with an overview of the LUT-based design paradigm and its two primary variants: inverse design (finding design parameters that meet the specifications) and forward evaluation (sweeping design parameters to search the design space). In support of the latter, the core of our work focuses on improving the accuracy and speed of LUT access, enabling millions of queries within seconds on a standard computer. Large improvements over prior art are enabled using enhanced interpolation methods, which allow for a relatively large LUT grid spacing (hence small memory footprint) and yet accurate parameter lookup. We evaluate the efficacy of the proposed methods using two classical analog circuits, a bandgap reference and a folded cascode amplifier. In the bandgap example, we observe less than 1 ppm error between the LUT-predicted temperature coefficient and circuit simulation. In the folded-cascode example, one million design points are generated in only 4 seconds, providing the designer with useful maps that delineate the reachability of certain target specifications.