With the increasing demand for convolutional neural networks (CNNs) in many edge computing scenarios and resource-limited settings, researchers have made efforts to apply lightweight neural networks on hardware platforms. While binarized neural networks (BNNs) perform excellently in such tasks, many implementations still face challenges such as an imbalance between accuracy and computational complexity, as well as the requirement for low power and storage consumption. This paper first proposes a novel binary convolution structure based on the time domain to reduce resource and power consumption for the convolution process. Furthermore, through the joint design of binary convolution, batch normalization, and activation function in the time domain, we propose a full-BNN model and hardware architecture (Model I), which keeps the values of all intermediate results as binary (1 bit) to reduce storage requirements by 75%. At the same time, we propose a mixed-precision BNN structure (model II) based on the sensitivity of different layers of the network to the calculation accuracy; that is, the layer sensitive to the classification result uses fixed-point data, and the other layers use binary data in the time domain. This can achieve a balance between accuracy and computing resources. Lastly, we take the MNIST dataset as an example to test the above two models on the field-programmable gate array (FPGA) platform. The results show that the two models can be used as neural network acceleration units with low storage requirements and low power consumption for classification tasks under the condition that the accuracy decline is small. The joint design method in the time domain may further inspire other computing architectures. In addition, the design of Model II has certain reference significance for the design of more complex classification tasks.

We propose a direct digital frequency synthesizer (DDFS) by using an error-controlled piecewise linear (PWL) approximation method. For a given function and a preset max absolute error (MAE), this method iterates continuously from right to left within the input interval, dividing the entire interval into multiple segments. Within each segment, the least squares method is used to approximate the objective function, ensuring that each segment meets the error requirements. Based on this method, We first implemented a set of DDFS under different MAE to study the relationship between SFDR and MAE, and then evaluated its hardware overhead. In order to increase the frequency of the output signal, we implement a multi-core DDFS using time interleaving scheme. The experimental results show that our DDFS has significant advantages in SFDR, using fewer hardware resources to achieve high SFDR. Specifically, the SFDR of proposed DDFS can reach 114 dB using 399 LUTs, 66 flip flops and 3 DSPs. More importantly, we demonstrate through experiments that proposed DDFS breaks the SFDR theoretical upper bound of DDFS based on piecewise linear approximation methods.

Nonlinear functions are widely used as activation functions in artificial neural networks, which have a great impact on the fitting ability of artificial neural networks. Due to the complexity of the activation function, the computation of the activation function and its derivative requires a lot of computing resources and time during training. In order to improve the computational efficiency of the derivatives of the activation function in the back-propagation of artificial neural networks, this paper proposes a method based on piecewise linear approximation method to calculate the derivative of the activation function. This method is hardware-friendly and universal, it can efficiently compute various nonlinear activation functions in the field of neural network hardware accelerators. In this paper, we use least squares to improve a piecewise linear approximation calculation method that can control the absolute error and get less number of segments or smaller average error, which means fewer hardware resources are required. We use this method to perform a segmented linear approximation to the original or derivative function of the activation function. Both types of activation functions are substituted into a multilayer perceptron for binary classification experiments to verify the effectiveness of the proposed method. Experimental results show that the same or even slightly higher classification accuracy can be achieved by using this method, and the computation time of the back-propagation is reduced by 4–6% compared to the direct calculation of the derivative directly from the function expression using the operator encapsulated in PyTorch. This shows that the proposed method provides an efficient solution of nonlinear activation functions for hardware acceleration of neural networks.

Hyperspectral images, characterized by rich spectral information, enable precise pixel-level classification and are thus widely employed in remote sensing applications. Although convolutional neural networks (CNNs) have demonstrated effectiveness in hyperspectral image processing, their limited receptive fields constrain their capacity to capture long-range dependencies. Transformers excel at modeling long-range features for hyperspectral image classification (HSIC). Yet, they often overlook effective representation of local spectral–spatial characteristics while incurring computational redundancy from numerous classification-irrelevant tokens. To address these challenges, we propose EDTST, a state-of-the-art Vision Transformer architecture specifically designed for efficient hyperspectral image classification. The model utilizes a large-kernel 3D convolution block to extract deep spectral–spatial features. A 2D convolution block further refines these features, followed by a novel attention mechanism with dynamic token pruning that substantially reduces the computational load by focusing on the most pertinent features. The process concludes with an adaptive average pooling layer and a fully connected layer for classification. Extensive experiments on four standard hyperspectral datasets demonstrate that EDTST achieves the highest classification accuracy, with a notable 3% improvement in overall accuracy on the WHU-Hi-HanChuan dataset, while requiring the shortest training and inference time among all compared state-of-the-art models from the past three years. These results validate the efficacy of our approach in achieving superior performance with markedly improved computational efficiency.

Deep learning techniques have been widely investigated as an effective method for signal measurement in recent years. However, most existing deep learning-based methods still face difficulty in deploying on embedded platforms and perform poorly in real-time applications. To address this, this paper develops two accelerators, as the core of the signal measurement system, for intelligent signal processing. Firstly, by introducing the idea of automated framework, we propose a simplest deep neural network (DNN)-based hardware structure, which automatically maps algorithms to hardware modules, supports configurable parameters, and has the advantage of low latency, with an average inference time of only 3.5 μs. Subsequently, another accelerator is designed with the efficient hardware structure of the long short-term memory (LSTM) + DNN model, demonstrating outstanding performance with a classification accuracy of 98.82%, mean absolute error (MAE) of 0.27°, and root mean square errors (RMSE) of 0.392° after model compression. Moreover, parallel optimization strategies are exploited to further reduce latency and support simultaneous frequency and direction measurement tasks. Finally, we test the actual collected signal data on the XCVU13P field programmable gate array (FPGA). The results show that the time of inference saves 28–31% for the DNN model and 71–73% for the LSTM + DNN model compared to running on graphic processing unit (GPU). In addition, the parallel strategies further decrease the delay by 23.9% and 37.5% when processing continuous data. The FPGA-based and deep learning-assisted hardware accelerators significantly improve real-time performance and provide a promising solution for signal measurement.

Angle of arrival (AOA) estimation and instantaneous frequency measurement (IFM) are important aspects of radar, communication, and electronic warfare, and there is an urgent need to find intelligent solutions that are faster and more accurate than traditional methods. Currently, deep learning (DL) has increasingly strong learning and feature extraction capabilities, which brings new opportunities to the field of electromagnetic signal processing. However, the models in DL have a large number of parameters, high storage requirements, and long computational latency, and not practical for deploying applications on resource-limited devices. In this paper, we build a complete AOA and IFM system for the first time, taking advantage of microwave photonics (MWP) technology, DL, and features of field programmable gate array (FPGA). Then, a novel hardware-friendly pruning-quantization-iteration compression (PQIC) algorithm is proposed for the post-processing of MWP signal measurement applications. By reducing the data width from 32 bits to 4 bits, the compressed algorithm reduces parameter storage requirements and hardware implementation complexity with negligible performance loss. Finally, we deploy the acceleration system and test the actual collected signal data on FPGA while running 200 MHz. The results show that with a 14× model compression and a 3.99× reduction in operations, the accuracy of AOA reaches 98.82%, with the mean absolute error (MAE) of 0.27°. More importantly, the running latency is only 20.78 μs, meeting the real-time processing requirements of MWP signal processing. It is also applicable to real-world signal intelligence processing and demonstrates superior performance compared to other existing algorithms in this field.