Recently, thin-film transistor based-ISFETs with the dual-gate (DG) structures have been proposed, in order to beat the Nernst response of the standard ISFET, utilizing diverse organic or inorganic materials. The immutable Nernst response can be dramatically transformed to an ultra-sensing margin, with the capacitive-coupling arisen from the DG structure. In order to advance this platform, we here embedded the ultra-thin body (UTB) into the DG ISFET. The UTB of 4.3 nm serves to not only increase its sensitivity, but also to strongly suppress the leakage components, leading to a better stability of the DG ISFET. In addition, we first provide a comprehensive analysis of the body thickness effects especially how the thick body can render the degradation in the device performance, such as sensitivity and stability. The UTB DG ISFET will allow the ISFET-based biosensor platform to continue enhancement into the next decade.

This study evaluated the memristive switching characteristics of a biomaterial solid polymer electrolyte (SPE) chitosan-based memristor and confirmed its artificial synaptic behavior with analog switching. Despite the potential advantages of organic memristors for high-end electronics, the unstable multilevel states and poor reliability of organic devices must be overcome. The fabricated Ti/SPE-chitosan/Pt-structured memristor has stable bipolar resistive switching (BRS) behavior due to a cation-based electrochemical reaction between a polymeric electrolyte and metal ions and exhibits excellent endurance in 5 × 10² DC cycles. In addition, we achieved multilevel per cell (MLC) BRS I-V characteristics by adjusting the set compliance current (I_cc) for analog switching. The multilevel states demonstrated uniform resistance distributions and nonvolatile retention characteristics over 10⁴ s. These stable MLC properties are explained by the laterally intensified conductive filaments in SPE-chitosan, based on the linear relationship between operating voltage margin (ΔV_switching) and I_cc. In addition, the multilevel resistance dependence on I_cc suggests the capability of continuous analog resistance switching. Chitosan-based SPE artificial synapses ensure the emulation of short- and long-term plasticity of biological synapses, including excitatory postsynaptic current, inhibitory postsynaptic current, paired-pulse facilitation, and paired-pulse depression. Furthermore, the gradual conductance modulations upon repeated stimulation by 10⁴ electric pulses were evaluated in high stability.

This study proposes a hybrid electric double layer (EDL) with complementary metal-oxide semiconductor (CMOS) process compatibility by stacking a chitosan electrolyte and a Ta₂O₅ high-k dielectric thin film. Bio-inspired synaptic transistors with excellent electrical stability were fabricated using the proposed hybrid EDL for the gate dielectric layer. The Ta₂O₅ high-k dielectric layer with high chemical resistance, thermal stability, and mechanical strength enables CMOS-compatible patterning processes on biocompatible organic polymer chitosan electrolytes. This technique achieved ion-conduction from the chitosan electrolyte to the In-Ga-Zn oxide (IGZO) channel layer. The on/off current ratio, subthreshold voltage swing, and the field-effect mobility of the fabricated IGZO EDL transistors (EDLTs) exhibited excellent electrical properties of 1.80 × 10⁷, 96 mV/dec, and 3.73 cm²/V·s, respectively. A resistor-loaded inverter was constructed by connecting an IGZO EDLT with a load resistor (400 MΩ) in series. This demonstrated good inverter action and responded to the square-wave input signals. Synaptic behaviours such as the hysteresis window and excitatory post-synaptic current (EPSC) variations were evaluated for different DC gate voltage sweep ranges and different AC gate spike stimuli, respectively. Therefore, the proposed organic–inorganic hybrid EDL is expected to be useful for implementing an extremely compact neural architecture system.

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin SiO 2 and Si 3 N 4 dielectric layers were used as engineered tunneling barriers. High- k dielectrics were used as charge trapping and blocking oxide layer to improve the program/erase speed. The VARIOT type tunneling barrier composed of oxide-nitride-oxide layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase in interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.