The field of flexible antennas is witnessing an exponential growth due to the demand for wearable devices, Internet of Things (IoT) framework, point of care devices, personalized medicine platform, 5G technology, wireless sensor networks, and communication devices with a smaller form factor to name a few. The choice of non-rigid antennas is application specific and depends on the type of substrate, materials used, processing techniques, antenna performance, and the surrounding environment. There are numerous design innovations, new materials and material properties, intriguing fabrication methods, and niche applications. This review article focuses on the need for flexible antennas, materials, and processes used for fabricating the antennas, various material properties influencing antenna performance, and specific biomedical applications accompanied by the design considerations. After a comprehensive treatment of the above-mentioned topics, the article will focus on inherent challenges and future prospects of flexible antennas. Finally, an insight into the application of flexible antenna on future wireless solutions is discussed.

Silicon channel ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric and silicon channel suffers from high write voltage, limited write endurance and long read-after-write latency. This is due to early IL breakdown and mobile charge injection at the ferroelectric-IL interface. Here, we demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricated IL-free FeFETs with 28nm channel length (Lg) and 126nm width under a thermal budget < 400 ⁰ C by integrating 5nm Hf _0.5 Zr _0.5 O ₂ (HZO) gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report a voltage memory window of 1.6V with a read current window ${I}_{\textit {LVT}}{/}{I}_{\textit {HVT}}$ of 10 ⁵ , write voltage of ±1.6V with 20ns pulses, instantaneous read-after-write latency < 300ns and a record high write endurance exceeding 10 ¹¹ cycles. This establishes the IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance last-level cache memory.

Pseudo-crossbar arrays using ferroelectric field effect transistor (FEFET) mitigates weight movement and allows in situ vector–matrix multiplication (VMM), which can significantly accelerate online training of deep neural networks (DNNs). However, the training accuracy of DNNs using conventional FEFETs is low because of the non-idealities, such as nonlinearity, asymmetry, limited bit precision, and limited dynamic range of the weight updates. The limited endurance of these devices degrades the training accuracy further. Here, we show a novel approach for designing the gate-stack of an FEFET analog synapse using a superlattice (SL) of ferroelectric (FE)/dielectric (DE)/FE. The partial polarization states are stabilized by harnessing the depolarization field from the DE spacer, which mitigates the weight update non-idealities. We demonstrate a 7-bit SL-FEFET analog synapse with improved weight update profile, resulting in 94.1% online training accuracy for MNIST handwritten digit classification task. The device uses an indium–tungsten–oxide (IWO) channel and back-end-of line (BEOL)-compatible process flow. The absence of low- ${k}$ interlayer (IL) results in high endurance (>10 ¹⁰ cycles), while the BEOL compatibility paves the way to high-density integration of pseudo-crossbar arrays and flexibility for neuromorphic circuit design.

In this article, an inkjet-printed circular-shaped monopole ultra-wideband (UWB) antenna with an inside-cut feed structure was implemented on a flexible polyethylene terephthalate (PET) substrate. The coplanar waveguide (CPW)-fed antenna was designed using ANSYS high-frequency structural simulator (HFSS), which operates at 3.04–10.70 GHz and 15.18–18 GHz (upper $K_u$ band) with a return loss < −10 dB and a VSWR < 2. The antenna, with the dimensions of 47 mm × 25 mm × 0.135 mm, exhibited omnidirectional radiation characteristics over the entire impedance bandwidth, with an average peak gain of 3.94 dBi. The simulated antenna structure was in good agreement with the experiment’s measured results under flat and bending conditions, making it conducive for flexible and wearable Internet of things (IoT) applications.

In this article, the optimization of printing properties on a new, flexible ceramic substrate is reported for sensing and antenna applications encompassing internet of things (IoT) devices. E-Strate^® is a commercially available, non-rigid, thin ceramic substrate for implementing in room temperature and high-temperature devices. In this substrate, the printing parameters like drop spacing, number of printed layers, sintering temperature, and sintering time were varied to ensure an electrically conductive and repeatable pattern. The test patterns were printed using silver nanoparticle ink and a Dimatix 2831 inkjet printer. Electrical conductivity, high-temperature tolerance, bending, and adhesion were investigated on the printed samples. The three-factor factorial design analysis showed that the number of printed layers, sintering temperature, sintering time, and their interactions were significant factors affecting electrical conductivity. The optimum printing parameters for the thin E-Strate^® substrate were found to be 20 μm drop spacing, three layers of printing, and 300 °C sintering temperature for 30 min. The high-temperature tolerance test indicated a stable pattern without any electrical degradation. Repetitive bending, adhesion test, and ASTM tape tests showed adequate mechanical stability of the pattern. These results will provide insight for investigators interested in fabricating new IoT devices.

We demonstrate a gate-all-around (GAA) nanosheet FET featuring an atomic layer-deposited (ALD) tungsten (W)-doped indium oxide (In₂O₃), or indium tungsten oxide (IWO), channel. A novel channel release process is developed, utilizing wet etching with an etching selectivity exceeding 10³ between the channel and a metal sacrificial layer (SL), enabling lithography-independent definition of the device channel length (L_Ch). The fabricated nanosheet FETs, with scaled dimensions of L_Ch = 50 nm and W_Nanosheet = 30 nm, exhibit a high ON-state current (I_ON) of 815 μA/μm at V_DS = 1 V and V_G - V_T = 3.5 V, along with an ultralow OFF-state current (I_OFF) of 3 fA. These IWO-GAA nanosheet FETs are demonstrated to achieve exceptional threshold voltage stability under both positive (PBTI) and negative (NBTI) bias stress conditions, with the hero device achieving a record-low threshold voltage shift (ΔV_T) of 88 mV for a stress voltage of V_G - V_T = 2.6 V, corresponding to a stress field (E_Stress) of 5.4 MV/cm.