SM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high‐speed applications. This study proposes a CPU‐FPGA co‐designed architecture which offloads the SM3 function on field‐programmable gate array so that high throughput can be achieved. The architecture can execute the SM3 hash algorithm with 16 concurrent streams or more, which means that multiple data streams can be processed in parallel. This design is implemented on the Xilinx XCKU115‐flva1517‐2‐e device and Dell commercial server, and the throughput of this design can reach up to 35.5 Gbps when 16 individual SM3 modules are processed in parallel. The proposed architecture results in an excellent performance in the CPU‐FPGA‐coupled environment.

Software-defined networking (SDN) has attracted much attention since it was proposed. The architecture of the SDN data plane is also evolving. To support the flexibility of the data plane, the software implementation approach is adopted. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. However, completely implementing the data plane on hardware weakens the flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput. We offloaded a cached-rule table to the proposed accelerator and tested its performance with 100 GbE traffic. Compared with the software implementation, the evaluation result shows that the throughput can achieve a 600% improvement when processing small packets and a 100% increase in large packet processing, and the latency can be reduced by about 20× and 100×, respectively, when processing small packets and large packets.

In this paper, we design and implement a full-packet capture and network measurement (FPC-NM) system in a 20 Gbit/s network. The system has multiple functions, such as packet receiving, nanosecond timestamp, load balancing, data packet preprocessing, application layer protocol analysis, data packet storage, and log management. We design a timestamp module in FPGA that can add a timestamp to each captured packet, and the retrospective packet analysis can be done with 4 ns accuracy. As far as we know, this is the first time that nanosecond timestamp has been applied to FPC-NM system, which greatly improves the accuracy of security incident retrospective analysis. The experimental results show that the FPC-NM system can achieve 17 Gbit/s throughput and 160,000 connections per second under the premise of zero packet loss. By using LZ4 compression, the performance of our system for real-time compression and storage of traffic can achieve 10 Gbit/s. The system performance is improved by about 40% after software optimization including direct memory access buffer size adjustment and single instruction multiple data instruction set, which validates the practicability and effectiveness of our optimization method.