High-speed CMOS imaging sensors (CIS) normally have low sensitivity because of the large integration capacitance. They also have high noise because pixel circuits cannot implement correlated double sampling (CDS) to remove the pixel reset noise. For applications, such as micro-computed tomography (micro-CT), this is a major limitation. In this work, we developed a technique to achieve high sensitivity and low noise for high-speed CIS. To maximize the sensitivity, we designed a new capacitive transimpedance amplifier (CTIA) pixel with a tiny metal-oxide-metal capacitor. The pixel circuit also implements CDS. As a result, the temporal noise is greatly reduced, and the sensitivity improves dramatically. To compensate the mismatch of small integration capacitors across the pixel array, an on-chip calibration scheme with in-pixel circuits is developed. Fully differential column circuits are designed to suppress the power supply injection in the large array of high-speed column circuits. A successive-approximation analog-to-digital (SAR ADC) is designed to achieve 10-bit resolution and to fit in the 15-μm column pitch. For testing modes, column circuits are configured into a two-step ADC to provide 13-bit dynamic range. The 256 × 256 CIS design is fabricated in a 0.18-μm CMOS process. The imager samples up to 1500 fps. The pixel integration capacitor is 0.7 fF, which enables 68.5 V/lux · s sensitivity under the white illumination. The CIS temporal noise is 13.6e^-. This sensitivity and noise performances are much better than previous high-speed CIS benchmark designs. Running at 1500 fps, the CIS can capture recognizable images with illumination down to 1 lux. The on-chip calibration suppresses the fixed-pattern noise lower than 0.52%. The prototype chip consumes 390 mW of power.

Microelectrode array (MEA) can be used in the study of neurodegenerative diseases by monitoring the chemical neurotransmitter release and the electrical potential simultaneously at the cellular level. Currently, the MEA technology is migrating to more electrodes and higher electrode density, which raises power and area constraints on the design of acquisition IC. In this paper, we report the design of a 200-channel dual-mode acquisition IC with highly efficient usage of power and area. Under the constraints of target noise and fast settling, the current channel design saves power by including a novel current buffer biased in discrete time (DT) before the TIA (transimpedance amplifier). The 200 channels are sampled at 20 kS/s and quantized by column-wise SAR ADCs. The prototype IC was fabricated in a 0.18 μm CMOS process. Silicon measurements show the current channel has 21.6 pA _rms noise with cyclic voltammetry (CV) and 0.48 pA _rms noise with constant amperometry (CA) while consuming 12.1 μW. The voltage channel has 4.07 μVrms noise in the bandwidth of 100 kHz and 0.2% nonlinearity while consuming 9.1 μW. Each channel occupies 0.03 mm ² area, which is among the smallest.

The design of an ambient radio frequency (RF) energy harvesting system is introduced to replace the battery of the mass Internet-of-Things devices. This system can achieve high sensitivity with high efficiency over a wide input power range by optimizing the differential-drive cross-coupled (DDCC) rectifier and the load. The impedance of the dual-band four-port loop antenna array is directly conjugated to match with the rectifier, which reduces insertion loss of the matching network to improve efficiency. At 915 and 945 MHz for ISM and GSM bands, the rectenna can achieve high sensitivity of −30 dBm with 22% and 24% efficiency, high efficiency of 65% and 48% with −20-dBm input power, and a wide input power range from −30 to −18 dBm with 22–65% and 24–48% efficiency. The dual-band design explores the frequency diversity to harvest more RF energy from the environment, while the cross-shaped antenna array utilizes the space diversity to harvest RF energy from different directions with a compact size of $0.15\lambda \times 0.15\lambda $ per antenna element (where $\lambda $ is the free space wavelength at 915 MHz). This new harvesting system can provide output dc power of 21.4 and $2.95~\mu \text{W}$ in real-world outdoor and indoor ambient environments, respectively.

The linearity of a high-resolution pipelined analog- to-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolation- based digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35 3.3 V CMOS process. The ADC samples at 20 MS/s. The calibration improves the ADC DNL and INL from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590 kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB respectively. The 11.8-ENOB 20 MS/s ADC consumes 56.3 mW power with 3.3 V supply. The 0.78 pJ/step figure-of-merit (FOM) is low for designs in 0.35 CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8 dB due to the slow settling of the first pipeline stage.

A systematic design methodology for high-performance gain-boosted opamps (GBOs) is presented. The methodology allows the optimization of the GBO in terms of ac response and settling performance and is incorporated into an automatic computer-aided design (CAD) tool, called GBOPCAD. Analytic equations and heuristics are first used by GBOPCAD to obtain a sizing solution close to the global optimum. Then, simulated annealings are used by GBOPCAD to find the global optimum. A sample opamp is designed by this tool in a 0.6-/spl mu/m CMOS process. It achieves a dc gain of 80 dB, a unity-gain bandwidth of 836 MHz with 60/spl deg/ phase margin and a 0.0244% settling time of 5 ns. The sample/hold front-end of a 12-bit 50-MSample/s analog-digital converter was implemented with this opamp. It achieves a signal-to-noise ratio of 81.9 dB for a 8.1-MHz input signal.