Industry 4.0 considers the combinations of Internet of Things, computing and communication infrastructure, sensors, and artificial intelligence (AI) to provide predictive maintenance and process optimization. These benefits are very relevant to the semiconductor industry, where high reliability and low operating costs are critical for a business’ success. Analyzing the state-of-the-art of the projects that present the implementation of the fourth industrial revolution in semiconductor companies, we noticed mainly two branches of initiatives: (i) articles that explain the final achievements, not detailing how they were assembled and structured; (ii) articles that detail a part of the industry ecosystem, for example, approaching only the communication system or AI algorithms. In this context, this article proposes an I4.0 Pilot as a compilation of lessons learned during an end-to-end development of a reference design applied to a semiconductor packaging and test company. We explore the requirements of clean rooms and information related to sensors and data acquisition boards, in addition to performance details and configurations pertaining to visualization tools and warning notifications. The main contribution appears in presenting the advantages of adopting flexible decisions in the pilot to enable the best characteristics for a final expandable solution. Our final idea is to emphasize the importance of having a pilot project without significant expenses, presenting the reader with the acquired knowledge, and how they can benefit from it.

Cloud, IoT, big data, and artificial intelligence are currently very present in the industrial and academic areas, being drivers of technological revolution. Such concepts are closely related to Industry 4.0, which can be defined as the idea of a flexible, technological, and connected factory, encompassing the shop floor itself and its relationship between workers, the chain of supply, and final products. Some studies have already been developed to quantify a company’s level of maturity within the scope of Industry 4.0. However, there is a lack of a global and unique index that, by receiving as input how many implemented technologies a company has, enables its classification and therefore, comparison with other companies of the same genre. Thus, we present the I4.0I (Industry 4.0 Index), an index that allows companies to measure how far they are in Industry 4.0, enabling competitiveness between factories and stimulating economic and technological growth. To assess the method, companies in the technology sector received and answered a questionnaire in which they marked the technologies they used over the years and the income obtained. The results were used to compare the I4.0I with the profit measured in the same period, proving that the greater the use of technology, the greater the benefits for the company.

This paper presents a compression algorithm for power quality (PQ) signals, which does not separate the signal into stationary and transient components. The proposed algorithm is composed of a number of different compression techniques which are combined to improve both compression ratio and total computing time. This method is based on a sequence of three phases. The first phase transforms the signal to the frequency domain using the FFT algorithm. In a second phase the signal is approximated by a polynomial approximation algorithm, which is finally compressed by a lossless compression algorithm. The proposed method is characterized by high compression ratio and low computational cost, making its implementation suitable for embedded systems.

This paper presents the integration of a Power Quality (PQ) data compression/decompression Application Specific Integrated Circuit (ASIC) into an AC power quality analyzer. The integration of the ASIC improves substantially the system data storage capabilities. The paper describes the compression algorithms implemented in dedicated CMOS circuitry. Compression results obtained from real power line measurements are herein shown to prove the effectiveness of our compression/decompression ASIC. This chip has a die area of 15mm ² , more than 400k 2-input logic gates equivalent, and 10 SRAM modules, all integrated into a 180nm digital CMOS technology. To the best of our knowledge this is the first lossy compression/decompression ASIC design for registering power quality trends over time, which is also compliant with the IEC 61000-4-30 standard accuracy requirements, fully tested and functional in a Class A system hardware PQ analyzer.