This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled.

This paper surveys the different design issues, from mathematical model to silicon, involved in the design of analog CMOS integrated circuits for the generation of chaotic behavior.

This paper presents a fully integrated low-power 130-nm CMOS transceiver tailored to the Bluetooth low energy (BLE) standard. The receiver employs a passive front-end zero-IF architecture, which is directly driven by a quadrature voltage-controlled oscillator (QVCO) without any buffering stage. The QVCO, embedded in a fractional-$N$ phase-locked loop (PLL), employs a passive $RC$ network to cancel the parasitic magnetic coupling between the two cores so as to keep the quadrature phase error below 1.5$^{\circ}$. The PLL exhibits a high loop bandwidth of 1 MHz to sufficiently reduce the frequency pulling effects due to close-by interferers. The transmitter uses a direct-modulation Gaussian frequency-shift keying scheme in which small PMOS-based cells modulate the output signal of one of the cores of the QVCO. In the baseband section, the transceiver employs a 4-bit phase-domain ADC based on novel linear-combiner topology to generate the required phase rotations. The proposed combiner operates in current domain and does not employ resistors, leading to a power- and area-efficient demodulator implementation. The complete receiver achieves a sensitivity of ${-}$ 81.4 dBm and fulfills the BLE requirements on interference blocking. It consumes 1.1 mW from a 1.0-V supply and has a similar power efficiency as recent super-regenerative receivers that are much more susceptible to interferers. The transmitter delivers 1.6-dBm output power to a differential 100 $\Omega$ and consumes 5.9 mW, which implies a total efficiency of 24.5%.

This paper presents an RF energy harvester embedded in a low-power transceiver (TRX) front-end. Both the harvester and the TRX use the same antenna and operate at the same frequency of 2.4 GHz. To decouple the harvester from the TRX, different concepts are proposed regarding the transmitter (TX) and receiver (RX). To avoid loading the TX, the harvester is decoupled with an nMOS switch that can be enabled with a start-up rectifier. Concerning the RX, the decoupling mechanism relies on the nonlinear input impedance of the main RF-DC converter. The harvester also includes a supply management circuit for over-voltage protection and charging energy storage devices with a constant current or voltage. The energy harvester has been co-integrated with the low power TRX in a 130 nm CMOS process and achieves a measured peak power conversion efficiency of 15.9%. For input power levels of at least -9 dBm, it is able to charge up a supply capacitor to a regulated voltage of 1.34 V. The impact of the harvester on the TRX performance is measured with respect to an identical TRX front-end without harvester, showing little impact on the TRX performance. Both TX output power and RX noise figure are degraded by less than 0.5 dB. As an additional feature, the start-up rectifier is also used for demodulation of On-Off-Keying (OOK) signaling, which can be used as a secondary wake-up channel. Since the required area for the harvester is only 0.019 mm ² (≈ 2% of the total active TRX area), it can be added to the TRX at almost no cost.

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.