Time (or clock) synchronization is a large and vital field of research, as synchronization is a precondition for many applications. A few example applications are distributed data acquisition, distributed databases, and real-time communication. First, this survey paper introduces the research area of time synchronization and emphasizes its relation to other research areas. Second, we give an overview of the state-of-the-art of time synchronization. Herein, we discuss both established protocol and research approaches. We analyze all techniques according to three criteria: used estimation algorithm, achievable synchronization accuracy, and the experimental conditions. In our opinion, this analysis highlights potential improvements. The most important question in this survey is as follows: which estimation method can be used to achieve which accuracies under which conditions? The intention behind this is to identify estimation methods that are particularly worth considering, as these already achieve good results in the wireless area but have not yet been examined in the wired area (and vice versa). This survey paper differs from other surveys in particular through the consideration of wireless and wired synchronization and the focus on estimation algorithms and their achievable accuracy.

Clock synchronization protocols such as the precision time protocol (PTP), which are used to synchronize components of distributed systems, are fundamental to enable timed and coordinated activities, e.g., in real-time applications within the industrial Internet of things (IIoT). In theory, PTP is able to achieve a precision on the order of nanoseconds. However, its practical accuracy remains limited by packet delay variations. In this paper, we hence present a novel approach to increase the synchronization precision of PTP. Our approach (PTP-LP) relies on PTP to obtain precise hardware timestamps taken during multiple synchronization periods. These timestamps establish the constraints for a Linear Programming (LP) solver that is used to estimate the clock differences between devices. Moreover, we propose the heuristic PTP-H that achieves comparable accuracy but is less computationally complex. We evaluate PTP-LP and PTP-H in comparison with two state-of-the-art approaches under various conditions in terms of clock stabilities and packet delay distributions. PTP-LP and PTP-H are fully compatible with existing standards and show to be in particular robust to varying packet delays. Especially, PTP-LP outperforms previous approaches in presence of a stable hardware clock and unknown non-negligible network delay, which are both realistic working conditions.

The superconducting stellarator Wendelstein 7-X (W7-X) started plasma operation in December 2015 after the commissioning phase of the machine. The main technical and diagnostic systems have been finished successfully. The timing system is an important part of the Control, Data Acquisition and Communication systems of W7-X. The first version of the TTE-system is in routine operation at the W7-X experiment. Since 2004 it has been used for the commissioning of the control and data acquisition components, and also for the stellarator WEGA. The commission of the second version of the TTE-system is still on going and planned to be finished end of 2016. Starting with an introduction of the TTE-system of W7-X, this contribution describes the main features of the TTE-system. The actual state of the TTE-system and the network topology will be presented. Finally, first experiences of W7-X operational phase OP1.1 related to the TTE-system are discussed.

Clock synchronization is an important issue in wired and wireless networks as a common time basis is essential for coordinated activities of nodes in distributed systems. Typical applications demanding precise synchronization are Industrial Internet scenarios having real-time constraints, Wireless Sensor Networks (WSNs) where the nodes communicate only for a short period and can sleep the remaining time to save energy, approaches based on Time Division Multiple Access (TDMA), and distributed measurements. The basic idea of our approach is to estimate all delays in a network. As a result, we can estimate the one-way delay between a reference node and all other nodes in the network. Consequently, we can use broadcast messages to synchronize the entire network. Utilizing a novel measurement method and a Java prototype implementation, we show that our approach achieves a high precision (≈ 123 μβ). Furthermore, it is highly scalable and platform independent. As our synchronization approach operates at the application layer, it is suitable for both wired and wireless networks.

Recently, there has been the arise of latency-sensitive IoT applications, e.g., in the field of telemedicine or Industrial Internet. Such applications have stringent latency requirements. The entire end-to-end latency between two devices is composed of several individual latencies: the software latency of the application, the software latency in the networking stack, the hardware latency on wire, and the hardware latency in switches. The hardware latencies are relatively invariant (constant). Contrary, the software latency is highly variant and thus hard to determine. However, the software-introduced latency is crucial for latency-sensitive applications, since the end-to-end latency equals the sum of all latencies between two devices. In the literature, different investigations based on simulations as well as practical test-beds using specialized hardware are proposed. In contrast, we propose a novel method using no specialized hardware that precisely estimates the latency in the networking software (precision: approx. 144µs). Our approach bases on the measurement of round-trip times between several devices and solving the resulting system of equations to estimate the latency of every individual device. Compared to the state-of-the-art the proposed method has also several advantages regarding scalability and resiliency.

The concept of hardware-software codesign allows to cope with the increasing complexity of very large scale integration (VLSI) systems. This concept is based on design space exploration (DSE), which means the systematic altering of design parameters (e.g., parallelization, serialisation, implementation of a functionality in software or hardware) to improve the final design. Existing DSE approaches work with high-level descriptions (e.g., SystemC) of the functionality. However, if existing systems (or submodules of those) shall be reused, only a synthesizable register-transfer level (RTL) description of these functionalities is necessarily given. Consequently, the RTL modules cannot be considered during the DSE. We propose an approach to this problem of reasonable practical relevance. To conduct the DSE, we estimate the software execution time of a functionality based on its RTL description. We show in an evaluation that this estimation is possible based on RTL code. In addition, we propose several suggestions to mitigate the problem that the software execution time of a functionality is highly dependent on the input data, which are often unknown at design time.