Nonvolatile memory structures using Ge nanocrystals embedded in ${\mathrm{SiO}}_2$ have been characterized by room and low temperature current–voltage and capacitance–voltage measurements. The Ge nanocrystals have been fabricated by low pressure chemical vapor deposition process which is shown to be well suited for a real control of the tunnel oxide thickness. The deposition conditions allow a separate control of $\mathrm{nc-}\mathrm{Ge}$ density and size. Using capacitance–voltage characterizations on nonvolatile memory structures, we have measured the charging and discharging kinetics of holes for tunnel oxides in the range 1.2–2.5 nm. Using current–voltage measurements and simulations, we have also shown that $\mathrm{nc-}\mathrm{Ge}$ are at the origin of a tunnel-assisted current. Simulations have demonstrated that the hole’s charging effects strongly reduce the current density across the nonvolatile memory structure. Combined with a good control of $\mathrm{nc-}\mathrm{Ge}$ properties, the use of Ge dots with large diameters $\text{(>10\hspace{0.5em}}\mathrm{nm})$ seems to be a promising way for p-type memory applications.

This paper reports ultrahigh-sensitive and ultralow-power CMOS compatible pH sensors that are developed in the back-end-of-line (BEOL) of industrial 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) transistors. Fabricating the sensing gate and the control gate of the sensors in a capacitive divider circuit, CMOS compatible pH sensors are demonstrated where the front gate bias is applied through a control gate rather than a bulky reference electrode. On the other hand, the strong electrostatic coupling between the front gate and the back gate of FDSOI devices provide an intrinsic signal amplification feature for sensing applications. Utilizing an atomic layer deposited aluminum oxide (Al ₂ O ₃ ) as a pH sensing film, pH sensors having a sensitivity of 475 mV/pH and 730 mV/pH in the extended gate and BEOL configuration, respectively, are reported. Sensitivities of both configurations are superior to state-of-the-art low power ion-sensitive field-effect transistors. The small sensing area and the FDSOI-based low power technology of the device make the sensors ideal for the IoT market. The proposed approach has been validated by TCAD simulation, and demonstrated through experimental measurements on proof-of-concept extended gate pH sensors and on sensors that are developed in the BEOL of industrial UTBB FDSOI devices.

The epitaxy of III-V semiconductors on silicon substrates remains challenging because of lattice parameter and material polarity differences. In this work, we report on the Metal Organic Chemical Vapor Deposition (MOCVD) and characterization of InAs/GaAs Quantum Dots (QDs) epitaxially grown on quasi-nominal 300 mm Ge/Si(001) and GaAs(001) substrates. QD properties were studied by Atomic Force Microscopy (AFM) and Photoluminescence (PL) spectroscopy. A wafer level µPL mapping of the entire 300 mm Ge/Si substrate shows the homogeneity of the three-stacked InAs QDs emitting at 1.30 ± 0.04 µm at room temperature. The correlation between PL spectroscopy and numerical modeling revealed, in accordance with transmission electron microscopy images, that buried QDs had a truncated pyramidal shape with base sides and heights around 29 and 4 nm, respectively. InAs QDs on Ge/Si substrate had the same shape as QDs on GaAs substrates, with a slightly increased size and reduced luminescence intensity. Our results suggest that 1.3 μm emitting InAs QDs quantum dots can be successfully grown on CMOS compatible Ge/Si substrates.

This work demonstrates an experimental microchannel solution to cool microelectronic chips with hot spots, using an integrated, yet non-intrusive technique. In microelectronics, approaches such as die thinning induce acute stress on cooling because it increases the hot spot phenomena and reduces chip bulk thickness that could be used for microchannels. In compact devices, heat must be removed using limited pumping power and cooling space. Microchannels etched in the backside of the chip, usually considered as an efficient cooling solution, are impracticable on highly thinned chips. This work experimentally investigates the cooling performance of a non-invasive and hot spot aware microchannel die that is in direct fluidic contact with the backside of the microelectronic chip. It also proposes a confinement-wise metric. A thermal resistance of 2.8 °C/W is achieved at a heat flux of 812 W/cm2 per heat source, for a total dissipated power of 20 W and a maximum allowed temperature rise of 55 °C. Such performance is obtained with only 19.2 kPa of pressure drop and 9.4 ml/min of flow rate, corresponding to a hydraulic power of only 3 mW and a coefficient of performance of 6 500. In addition, the complete chip stack, including the thinned chip, measures only 660 μm high. Therefore, backside cooling appears to be a promising compact and low consumption solution for compact electronic applications having confined hot spots.