Michał Tadeusiewicz

Prof. Michał Tadeusiewicz

Lodz University of Technology
orcid

Research Focus & Metrics

Academic Career Length

46Years (1981-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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7 December 2017 in IEEE Transactions on Instrumentation and Measurement
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MTMichał Tadeusiewicz
Michał Tadeusiewicz
Stanisław HałgasStanisław Hałgas
Stanisław Hałgas
This paper is devoted to local parametric fault diagnosis of nonlinear analog integrated circuits designed in a bipolar and CMOS technology. An algorithm is proposed that allows estimating values of the considered set of the parameters. The algorithm exploits a diagnostic test performed in a dc state, leading to output voltages measured in the circuit. Each of the output voltages is a parameterized function. A system of overdetermined equations fitting the parameterized functions to the data points is created. An efficient iterative method is developed for solving this overdetermined system of nonlinear equations exploiting the idea of the normal equation and a homotopy concept. It is implemented in the manner that allows operating with the functions not given in the explicit analytical form, which commonly occurs in real nonlinear circuits. For illustration, two examples are given, including a circuit with bipolar transistors and a CMOS circuit designed in a nanometer technology. They reveal the effectiveness of the proposed method.

1 September 1994 in Journal of Circuits, Systems and Computers
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MTMichał Tadeusiewicz
Michał Tadeusiewicz
KGKrzysztof Głowienka
Krzysztof Głowienka

27 April 2015 in IEEE Transactions on Instrumentation and Measurement
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MTMichał Tadeusiewicz
Michał Tadeusiewicz
Stanisław HałgasStanisław Hałgas
Stanisław Hałgas
This paper deals with multiple soft fault diagnosis of nonlinear analog circuits and offers a method that allows locating the faulty parameters and evaluating their values. The method works with a system of nonlinear algebraic test equations, which are not given in explicit analytical form, and actually may possess multiple solutions. The solutions are specified by one or several sets of the diagnostic parameter values that meet the test. To find the multiple solutions, an extended systematic search method has been developed. The diagnostic algorithm proposed in this paper exploits this method and brings a new concept for finding the actual solution. As a result, the diagnostic process is considerably improved. It can be applied to bipolar junction transistor and CMOS circuits manufactured in micrometer and nanometer technologies. In the last case, however, the transistors are characterized by intricate models (PSP 103 or BSIM 4). In consequence, the CPU time increases due to very complex sensitivity analyses of the circuits required by the diagnostic method. In such a case, the proposed approach is useful at the preproduction stage, where the CPU time is offline and not crucial. For illustration, two numerical examples are given.

29 March 2011 in International Journal of Circuit Theory and Applications
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MTMichał Tadeusiewicz
Michał Tadeusiewicz
Stanisław HałgasStanisław Hałgas
Stanisław Hałgas
MKMarek Korzybski
Marek Korzybski

1 January 2011 in Metrology and Measurement Systems
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MTMichał Tadeusiewicz
Michał Tadeusiewicz
Stanisław HałgasStanisław Hałgas
Stanisław Hałgas
Multiple Soft Fault Diagnosis of Nonlinear DC Circuits Considering Component Tolerances: This paper is devoted to multiple soft fault diagnosis of analog nonlinear circuits. A two-stage algorithm is offered enabling us to locate the faulty circuit components and evaluate their values, considering the component tolerances. At first a preliminary diagnostic procedure is performed, under the assumption that the non-faulty components have nominal values, leading to approximate and tentative results. Then, they are corrected, taking into account the fact that the non-faulty components can assume arbitrary values within their tolerance ranges. This stage of the algorithm is carried out using the linear programming method. As a result some ranges are obtained including possible values of the faulty components. The proposed approach is illustrated with two numerical examples.

25 July 2014 in Circuits, Systems, and Signal Processing
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MTMichał Tadeusiewicz
Michał Tadeusiewicz
AKAndrzej Kuczyński
Andrzej Kuczyński
Stanisław HałgasStanisław Hałgas
Stanisław Hałgas
This paper deals, for the first time, with catastrophic fault diagnosis of nonlinear analog circuits containing bipolar and MOS transistors having multiple operating points (DC solutions). The faults are cuts of some connecting paths and short-circuits of some pairs of points. Simulation-before-test approach is applied for detection and identification of a single catastrophic fault. To build a fault dictionary, a diagnostic test is arranged based on DC analysis. In the discussed circuits having multiple DC solutions, the tested output voltage may assume different values for fixed value of the input voltage. This fact considerably complicates the fault diagnosis. The crucial point of the proposed approach is tracing large number of nonlinear multivalued input–output characteristics at different values of circuit parameters within their tolerance ranges. For this purpose an efficient and fast algorithm is developed, based on the theory known under the name a linear complementarity problem. To illustrate the proposed approach and show its efficiency, four numerical examples are given.