Developing HW modules for standard platforms like PCs or embedded devices requires a complete system emulator availability to detect and fix bugs on developed HW, Operating Systems (OS) drivers and applications. This paper presents a set of plug-ins to an open-source CPU emulator that enables mixed simulations between platforms emulators and hardware (HW) modules described in SystemC. In this paper three plugins for QEMU are described: one for connecting TLM SystemC modules to any bus QEMU emulates, one for connecting SystemC to PCI bus for PC based platform and one plug-in for connecting SystemC to AMBA bus for ARM platforms. With this framework, it is possible to develop OS drivers at the same time HW is developed and final application tested running in this virtual platform.

The rapid evolution of Cloud-based services and the growing interest in deep learning (DL)-based applications is putting increasing pressure on hyperscalers and general purpose hardware designers to provide more efficient and scalable systems. Cloud-based infrastructures must consist of more energy efficient components. The evolution must take place from the core of the infrastructure (i.e., data centers (DCs)) to the edges (Edge computing) to adequately support new/future applications. Adaptability/elasticity is one of the features required to increase the performance-to-power ratios. Hardware-based mechanisms have been proposed to support system reconfiguration mostly at the processing elements level, while fewer studies have been carried out regarding scalable, modular interconnected sub-systems. In this paper, we propose a scalable Software Defined Network-on-Chip (SDNoC)-based architecture. Our solution can easily be adapted to support devices ranging from low-power computing nodes placed at the edge of the Cloud to high-performance many-core processors in the Cloud DCs, by leveraging on a modular design approach. The proposed design merges the benefits of hierarchical network-on-chip (NoC) topologies (via fusing the ring and the 2D-mesh topology), with those brought by dynamic reconfiguration (i.e., adaptation). Our proposed interconnect allows for creating different types of virtualised topologies aiming at serving different communication requirements and thus providing better resource partitioning (virtual tiles) for concurrent tasks. To further allow the software layer controlling and monitoring of the NoC subsystem, a few customised instructions supporting a data-driven program execution model (PXM) are added to the processing element’s instruction set architecture (ISA). In general, the data-driven programming and execution models are suitable for supporting the DL applications. We also introduce a mechanism to map a high-level programming language embedding concurrent execution models into the basic functionalities offered by our SDNoC for easing the programming of the proposed system. In the reported experiments, we compared our lightweight reconfigurable architecture to a conventional flattened 2D-mesh interconnection subsystem. Results show that our design provides an increment of the data traffic throughput of $9.5$% and a reduction of $2.2\times$ of the average packet latency, compared to the flattened 2D-mesh topology connecting the same number of processing elements (PEs) (up to 1024 cores). Similarly, power and resource (on FPGA devices) consumption is also low, confirming good scalability of the proposed architecture.

The number of cores per chip keeps increasing in order to improve performance while controlling the power. According to semiconductor roadmaps, future computing systems while reach the scale of 1 Tera devices in a single package. Firstly, such Tera-device systems will expose a large amount of parallelism that cannot be easily and efficiently exploited by current applications and programming models. Secondly, the reliability of Tera-device systems will become a critical issue. Finally, we need to simplify the design of such systems. TERAFLUX aims at providing a framework based on dataflow concepts that could provide a solution for all the three above challenges. We briefly present here our idea on the architectural support for the TERAFLUX execution model.

Moving from Petascale to Exascale computing necessitates optimizing the micro-architectural to increase the performance/power ratio of multicores (e.g., FLOPS/W). Future manycore processors will contain thousands of low-powered processing elements (kilo-core Chip Multi-Processors - CMPs) to support the execution of a large number of concurrent threads. While data-driven Program eXecution Models (PXMs) are gaining popularity due to the support they provide for thread communication, frequent data exchange among many concurrent threads puts stress on the underlying interconnect subsystem. This results in hotspots and high latency for data packet delivering. As a solution, we propose a scalable Software Defined Network-on-Chip (SDNoC) architecture for future manycore processors. Our design tries to merge the benefits of ring-based NoCs (i.e., performance, energy efficiency) with those brought by dynamic reconfiguration (i.e., adaptation, fault tolerance) while keeping the hard-wired topology (2D-mesh) fixed. To potentially accommodate different application and communication requirements, our interconnect allows mapping different types of topologies (virtual topologies). To allow the software layer to control and monitor the NoC subsystem, few customized instructions supporting a data-driven PXM are added to the core ISA. In experiments, we compared our lightweight reconfigurable architecture to a conventional 2D-mesh interconnection subsystem. Results show that our model allows savings of 39.4% of the chip area and up to 72.4% of the consumed power.

This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation speed, accuracy and model abstraction level, and are shown to be complementary. We apply the MUSA trace-based simulator for the initial sizing of vector register length, system-level cache (SLC) size and memory bandwidth. It has proven to be very efficient at pruning the design space, as its models enable sufficient accuracy without having to resort to highly detailed simulations. Then we apply gem5, a cycle-accurate micro-architecture simulator, for a more refined analysis of the performance potential of our reference SoC architecture, with models able to capture detailed hardware behavior at the cost of simulation speed. Furthermore, we study the network-on-chip (NoC) topology and IP placements using both gem5 for representative small- to medium-scale configurations and SESAM/VPSim, a transaction-level emulator for larger scale systems with good simulation speed and sufficient architectural details. Overall, we consider several system design concerns, such as processor subsystem sizing and NoC settings. We apply the selected simulation tools, focusing on different levels of abstraction, to study several configurations with various design concerns and evaluate them to guide architectural design and optimization decisions. Performance analysis is carried out with a number of representative benchmarks. The obtained numerical results provide guidance and hints to designers regarding SIMD instruction width, SLC sizing, memory bandwidth as well as the best placement of memory controllers and NoC form factor. Thus, we provide critical insights for efficient design of future HPC microprocessors.

Future exascale machines will require multi/many-core architectures able to energyciently run multi-threaded applications.\ud Data-flow execution models have demonstrated to be capable of improving execution performance by limiting the\ud synchronization overhead. This paper proposes to augment cores with a minimalistic set of hardware units and dedicated\ud instructions that allow energyciently scheduling the execution of threads on the basis of data-flow principles. Experimental\ud results show performance improvements of the system when compared with other techniques (e.g., OpenMP, Cilk)