Cancer and other gene related diseases are usually caused by a failure in the signaling pathway between genes and cells. These failures can occur in different areas of the gene regulatory network, but can be abstracted as faults in the regulatory function. For effective cancer treatment, it is imperative to identify faults and select appropriate drugs to treat the faults. In this paper, we present an extensible Max-SAT based automatic test pattern generation (ATPG) algorithm for cancer therapy. This ATPG algorithm is based on Boolean Satisfiability (SAT) and utilizes the stuck-at fault model for representing signaling faults. A weighted partial Max-SAT formulation is used to enable efficient selection of the most effective drug.

This paper presents a review of the aging mechanisms and lifetime estimation methodologies for medium and high voltage cross-linked polyethylene (XLPE) cables under harsh environmental service conditions, which are integral to the reliability and safety of modern electrical power systems. The article first briefly delves into the various aging mechanisms experienced by power cables, describing the physical and chemical processes that underlie the degradation of XLPE cable insulation over time. The discussion then extends to various life models: physical life models that describe material property changes under operational stresses; phenomenological life models and multi-stress models that consider the concurrent impact of multiple stressors on cable aging; and probabilistic and reliability lifetime models which introduce a statistical perspective to the remaining lifetime estimation, essential for risk assessment in power systems. The review also explores frequency-based life models that investigate the effects of operational frequencies on cable longevity. A significant focus is placed on enlargement laws and electrical treeing life models, shedding light on specific degradation phenomena pertinent to high voltage insulation. The paper next examines artificial intelligence (AI)-based life models, a cutting-edge approach that integrates traditional knowledge with advanced computational techniques such as machine learning and data analytics for enhanced prediction of cable life expectancy. Future research directions are also proposed in this paper, which proposes a finite element method-AI Assisted partial discharge (PD) Analysis and remaining useful lifetime (RUL) Estimation model for XLPE Cables. This comprehensive review aims to serve as an indispensable resource for engineers and researchers, offering a holistic understanding of the state-of-the-art and future directions in the domain of cable life estimation and prognostics.

Electric vehicles (EVs) are playing a pivotal role in transportation systems to conform to the rising exigencies for enhanced performance with safety and hindered environmental impact. Thus, to improve the efficiency and downsize the maintenance cost of EVs, an early fault diagnosis (FD) framework is crucial. Bearing and stator winding faults, which account for approximately 78% of induction machine (IM) incipient faults in EVs, remain rather elusive for conventional sensors to accurately classify them and their incipient values. To this end, this paper presents a novel Attention-enhanced Autoencoder-Gated Recurrent Unit (AAGRU) model that improves the accuracy and efficiency of fault analysis in IMs. Moreover, since bearing faults are usually captured through vibration sensors, which are expensive and require direct coupling with the IM, a hybrid signal re-constructor is devised based on merely stator current signals. The proposed model leverages Empirical Mode Decomposition (EMD), Fast Fourier Transform (FFT), and Discrete Wavelet Decomposition (DWT) to process the electric current data, which are then used by the AAGRU model to identify, detect, and classify the fault patterns. Experimental results demonstrate that the proposed model offers a 1%–6% improvement in fault detection and an 8%–28% improvement in inter-turn short-circuit fault severity classification relative to different shallow and deep-based benchmark models. The proposed model was also tested on different load conditions to ensure its applicability in practice.

In modern digital signal processing and graphics applications, the shifter is an important module, consuming a significant amount of delay. This brief presents an architectural optimization approach to synthesize a faster barrel shifter block, which can be useful to reduce the delay of the design without significantly increasing the area. We have divided the problem of generating the shifter into two steps: (i) timing-driven selection of multiple stages for merging, and (ii) the design of the merged stage. In our proposed method, we define the notion of dual merged stage, where two stages are merged and the triple merged stage, where three stages are merged into a single composite stage. These merged stages are identified by using a timing-driven algorithm and are used in conjunction with some single stages of the traditional barrel shifter. The use of these merged stages helps reduce the depth of the proposed barrel shifter architecture, thereby improving the delay. The timing-driven nature of our algorithm helps produce a faster implementation for the overall shifter block. We have evaluated the performance of our design by using a number of technology libraries, timing constraints and shifter bit-widths. Our experimental data shows that the shifter block generated by our algorithm is significantly faster (10.19% on average) than the shifter block generated by a commercially available datapath synthesis tool. These improvements were verified on placed-and-routed designs as well.

This paper presents a mixed-signal architecture for implementing Quantized Neural Networks (QNNs) using flash transistors to achieve extremely high throughput with extremely low power, energy and memory requirements. Its low resource consumption makes our design especially suited for use in edge devices. The network weights are stored in-memory using flash transistors, and nodes perform operations in the analog current domain. Our design can be programmed with any QNN whose hyperparameters (the number of layers, filters, or filter size, etc) do not exceed the maximum provisioned. Once the flash devices are programmed with a trained model and the IC is given an input, our architecture performs inference with zero access to off-chip memory. We demonstrate the robustness of our design under current-mode non-linearities arising from process and voltage variations. We test validation accuracy on the ImageNet dataset, and show that our IC suffers only 0.6% and 1.0% reduction in classification accuracy for Top-1 and Top-5 outputs, respectively. Our implementation results in a $\sim \boldsymbol {50}\times$ reduction in latency and energy when compared to a recently published mixed-signal ASIC implementation, with similar power characteristics. Our approach provides layer partitioning and node sharing possibilities, which allow us to trade off latency, power, and area amongst each other.