Ching-Che Chung received B.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1997 and 2003, respectively. From 2004 to 2008, he served as a postdoctoral researcher in the same university, working in system-on-chip design methodologies and high-speed interface circuit design. In August 2008, he joined the Computer Science and Information Engineering Department, National Chung Cheng University, Chia-Yi, Taiwan, where he is currently a professor. His research interests mainly include wireless and wireline communication systems, low-power and system-on-a-chip (SoC) design technology, mixed-signal IC design and sensor circuits design, artificial intelligence (AI) chip design, all-digital phase-locked loop, all-digital delay-locked loop, and its applications.
Research Keywords & Expertise
PLLs
hardware accelerators ...
Integrated Circuits
Fingerprints
14%
hardware accelerators for machine learning
5%
PLLs
Short Biography
Ching-Che Chung received B.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1997 and 2003, respectively. From 2004 to 2008, he served as a postdoctoral researcher in the same university, working in system-on-chip design methodologies and high-speed interface circuit design. In August 2008, he joined the Computer Science and Information Engineering Department, National Chung Cheng University, Chia-Yi, Taiwan, where he is currently a professor. His research interests mainly include wireless and wireline communication systems, low-power and system-on-a-chip (SoC) design technology, mixed-signal IC design and sensor circuits design, artificial intelligence (AI) chip design, all-digital phase-locked loop, all-digital delay-locked loop, and its applications.
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