With the coming of the 4th industrial revolution era, manufacturers produce high-tech products. As the production process is refined, inspection technologies become more important. Specifically, the inspection of a printed circuit board (PCB), which is an indispensable part of electronic products, is an essential step to improve the quality of the process and yield. Image processing techniques are utilized for inspection, but there are limitations because the backgrounds of images are different and the kinds of defects increase. In order to overcome these limitations, methods based on machine learning have been used recently. These methods can inspect without a normal image by learning fault patterns. Therefore, this paper proposes a method can detect various types of defects using machine learning. The proposed method first extracts features through speeded-up robust features (SURF), then learns the fault pattern and calculates probabilities. After that, we generate a weighted kernel density estimation (WKDE) map weighted by the probabilities to consider the density of the features. Because the probability of the WKDE map can detect an area where the defects are concentrated, it improves the performance of the inspection. To verify the proposed method, we apply the method to PCB images and confirm the performance of the method.

In a semiconductor manufacturing process, defect cause analysis is a challenging task because the process includes consecutive fabrication phases involving numerous facilities. Recently, in accordance with the shrinking chip pitches, fabrication (FAB) processes require advanced facilities and designs for manufacturing microcircuits. However, the sizes of the particle defects remain constant, in spite of the increasing modernization of the facilities. Consequently, this increases the particle defect ratio. Therefore, this study proposes a particle defect management method for the reduction of the defect ratio. The proposed method provides a kernel-density-based particle map that can overcome the limitations of the conventional method. The method consists of two phases. The first phase is the acquisition of cumulative coordinates of the defect locations on the wafer using the FAB database. Subsequently, this cumulative data is used to generate a particle defect map based on the estimation of kernel density; this map establishes the advanced monitoring statistics. In order to validate this method, we conduct an experiment for comparison with the previous industrial method.

In the post-fabrication process for semiconductors, it is critical to predict the yield. This process consists of a series of electrical and physical tests following semiconductor fabrication, tests that generate a significant volume of parametric data. While past research has investigated yield prediction using parametric test data, most studies have difficulty correctly predicting the low and high yield because of the wide range of variables and the large data set. Also, in the case of the packaging yield, prediction is inaccurate as this yield does not directly correlate with the parametric test data. Therefore, this study proposes a framework in which the packaging yield is classified using the parametric test data of the previous step of the packaging test. This study involves three stages. In the first, data preprocessing is conducted due to the large data set. To learn a data mining model using much more data, parametric test data generated in the die level need to be changed into the wafer level. In the second stage, a random forest algorithm is used to select significant variables affecting the packaging yield. Finally, the third stage uses a nonlinear support vector machine (SVM) to classify the low and high yield. Through the three stages, this study demonstrates that this proposed algorithm has a superior performance.