Light-emitting diodes (LEDs) are becoming increasingly ubiquitous. They can be found in illumination appliances, phones, TVs, advertising panels, dashboards, and traffic signals, among others. Most illumination applications are becoming LED based, mainly due to their long operational lifetime and high energy efficiency, which is nowadays higher than 100 lm/W [1]. Other benefits include enhanced sustainability, a compact form factor, easier maintenance, and lower cost. For these reasons, LED lighting is expected to have a market share of 84% in the general illumination market by 2030 [2]. However, there is another characteristic that is not being fully exploited: LEDs are capable of switching their light intensity at a rate that is imperceptible to the human eye. This property has been used for dimming purposes but can also be utilized in the opportunistic deployment of value-added services based on visible light communication (VLC).

This paper presents a multi-user Visible Light Communication (VLC)-based Internet of Things (IoT) system using multi band-Carrierless Amplitude and Phase (m-CAP) modulation for IoT applications. The proposed system uses a digital m-CAP modulator embedded in a ceiling LED light fixture and analog receivers, aiming at low-cost, low-power, and small-sized IoT devices. The performance was evaluated in terms of the filtering stage design and the usage of guard bands. Different pairs of emitter and receiver filters were considered. While Bessel and Butterworth analog filters were tested in the analog receiver, the digital m-CAP modulator pulse shaping filter considered raised cosine filters, as well as digital matched filters for the analog Bessel and Butterworth filters. Regarding the guard bands, two approaches were considered: either by using the raised cosine roll-off factor (bandwidth compression) or by suppressing the even bands. The Bit Error Rate (BER) performance was obtained by simulation. The usage of the Bessel filter in the receiver, along with a digital matched filter, proved to be the best solution, achieving a BER lower than ${10}^{-3}$ for an Eb/No of 6 dB, using a third-order filter. Furthermore, guard bands should be used in order to mitigate inter-band interference in order to have improved performance when multiple users intend to simultaneously communicate.

With an emphasis on the real-time implementation of a practical carrier-less amplitude and phase (CAP) receiver for visible light communication (VLC), this paper proposes a full-digital architecture for the $M$ -CAP receiver with synchronisation and adaptive blind equalisation. The architecture is mainly based on the observation that a CAP signal can be demodulated using a quadrature and amplitude (QAM) receiver with an added counterclockwise rotation operation. The proposed CAP receiver employs two digital phase-locked loops (DPLL) to realise the symbol timing and carrier synchronisation, which are the most critical issues in practical systems. With the constant-modulus algorithm (CMA) offering the benefit of decoupling carrier and symbol timing synchronisation, the receiver can blindly equalise the distorted signal at the output of symbol timing synchronisation. Finally, the performance of 4/16/64-CAP receivers, which are designed using this architecture and operates at 80/160/240 Mbit/s through a low-pass light-emitting diode (LED) with a 3-dB bandwidth of 7 MHz cascaded with three measured optical wireless channels, is evaluated by Monte Carlo simulations. Results show that the receiver architecture can successfully solve the symbol timing and carrier synchronisation problems and mitigate inter-symbol interference caused by LED and/or wireless channels. The design framework for a full-digital CAP receiver has been laid out in this paper.

Analysing the impact of noise sources on the random instantaneous delay of a basic CMOS delay element is important for understanding the performance of systems that employ them, like voltage controlled delay lines or buffered clock distribution networks. This paper presents a model for the analysis of noise induced jitter in CMOS delay cells and delay lines. Because the increasing switching noise levels is becoming a serious impairment to the reliable use of analogue controlled devices inside high frequency digital VLSI circuits, this work focus primarily on digitally controlled delay lines. For these circuits, the output capacitance and drivability of delay elements are key parameters for the design of low jitter delay lines. Simulation results are presented for a 0.35μm CMOS technology.

Jitter in CMOS technologies depend on several physical and design parameters, which are expected to change with scaling. Also, some parameters will have to change (by the introduction of enhancement techniques) in order to meet the desired performance goals for each new generation. The impact of each one of these parameters is here evaluated in order to give some insight on the jitter generation, amplification and coupling phenomena in actual and future designs. The work is based on AMS (0.8 um and 0.35 um) and UMC (180 nm and 130 nm) models for high performance, minimum sized transistors. Also, data from ITRS has been used to predict jitter dependency on the various parameters in deep-submicron CMOS generations.

This paper discusses the usage of visible light communication concepts for Electronic Shelf Labeling Devices (ESLD), using unmodified smart phones. Visible light communication enables novel and interesting approaches to the design of these devices, able to address application scenarios that have not yet been explored. Amongst these novel approaches, it is worthwhile highlighting the feasibility to offer easy integration of social networking concepts, and the inherent ability to explore communication means supported by the lighting installation. The achieved results show that these novel electronic shelf labeling devices are able to offer good quality of service support, with nearly optimal bit error rates under normal illumination levels.