Flip-chip interconnects made entirely from copper are promising candidates to overcome the intrinsic limits of solder-based interconnects and match the demand for increased current densities of high-performance microprocessors. To this end, dip-based all-copper interconnects have been demonstrated to be a viable approach to form electrical interconnects by sintering copper nanoparticles between the copper pillar and pad. However, the performance of this technology is limited by residual porosity of the copper joint formed between the pillar and the pad during sintering. Moreover, the applicability of this technology in the printed circuit board industry is constrained by thermomechanical stresses that arise from the sintering. Furthermore, the compatibility of the sintering approach with standard finishing layers used as diffusion-barrier layers to provide wetting and to prevent the oxidation of the pillar and pad surfaces is unknown. In this paper, we pursue the advancement of dipbased all-copper interconnect technology. We demonstrate the robustness of dip-transfer of copper paste for varying withdrawal velocities and typical nonuniformities in copper pillar heights. Moreover, we prove the applicability of this technology with fine pillar diameters and pitches down to 10 and 20 μm, respectively. In addition, we demonstrate reduced porosities of the copper joints by applying pressure during the bonding process at 200 °C. This densification leads to interconnects with four times the shear strength and half the electrical resistance compared to interconnects formed without the application of pressure. In addition, the bonding temperature is decreased to 160 °C by applying a novel copper paste formulation, reducing the thermomechanical stress in the assembly caused by the cooling from the sintering temperature. Finally, the compatibility of this technology with EPAG, ENIG, and ENEPIG finishing layers is demonstrated, with resulting shear strength of the interconnects above 70 MPa and electrical resistance comparable to the unfinished samples.

Artificial Intelligence in combination with the Internet of Medical Things enables remote healthcare services through networks of environmental and/or personal sensors. We present a remote healthcare service system which collects real-life data through an environmental sensor package, including binary motion, contact, pressure, and proximity sensors, installed at households of elderly people. Its aim is to keep the caregivers informed of subjects’ health-status progressive trajectory, and alert them of health-related anomalies to enable objective on-demand healthcare service delivery at scale. The system was deployed in 19 households inhabited by an elderly person with post-stroke condition in the Emilia–Romagna region in Italy, with maximal and median observation durations of 98 and 55 weeks. Among these households, 17 were multi-occupancy residences, while the other 2 housed elderly patients living alone. Subjects’ daily behavioral diaries were extracted and registered from raw sensor signals, using rule-based data pre-processing and unsupervised algorithms. Personal behavioral habits were identified and compared to typical patterns reported in behavioral science, as a quality-of-life indicator. We consider the activity patterns extracted across all users as a dictionary, and represent each patient’s behavior as a ‘Bag of Words’, based on which patients can be categorized into sub-groups for precision cohort treatment. Longitudinal trends of the behavioral progressive trajectory and sudden abnormalities of a patient were detected and reported to care providers. Due to the sparse sensor setting and the multi-occupancy living condition, the sleep profile was used as the main indicator in our system. Experimental results demonstrate the ability to report on subjects’ daily activity pattern in terms of sleep, outing, visiting, and health-status trajectories, as well as predicting/detecting 75% hospitalization sessions up to 11 days in advance. 65% of the alerts were confirmed to be semantically meaningful by the users. Furthermore, reduced social interaction (outing and visiting), and lower sleep quality could be observed during the COVID-19 lockdown period across the cohort.

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm² per tier. An active integrated circuit (IC) area of 4 cm² was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm². The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm² and 29 kW/cm³, respectively.