A phase-locked loop (PLL) is a nonlinear negative-feedback control system that synchronizes its output in frequency as well as in phase with its input. PLLs are now widely used for the synchronization of power-electronics-based converters and also for monitoring and control purposes in different engineering fields. In recent years, there have been many attempts to design more advanced PLLs for three-phase applications. The aim of this paper is to provide overviews of these attempts, which can be very useful for engineers and academic researchers.

The phase-locked loops (PLLs) are probably the most widely used synchronization technique in grid-connected applications. The main challenge that is associated with the PLLs is how to precisely and fast estimate the phase and frequency, when the grid voltage is unbalanced and/or distorted. To overcome this challenge, incorporating moving average filter(s) (MAF) into the PLL structure has been proposed in some recent literature. An MAF is a linear-phase finite-impulse-response filter, which can act as an ideal low-pass filter, if certain conditions hold. The main aim of this paper is to present the control design guidelines for a typical MAF-based PLL. The paper starts with the general description of MAFs. The main challenge associated with using the MAFs is then explained, and its possible solutions are discussed. The paper then proceeds with a brief overview of the different MAF-based PLLs. In each case, the PLL block diagram description is shown, the advantages and limitations are briefly discussed, and the tuning approach (if available) is evaluated. The paper then presents two systematic methods to design the control parameters of a typical MAF-based PLL: one for the case of using a proportional-integral (PI) type loop filter (LF) in the PLL, and the other for the case of using a proportional-integral-derivative (PID) type LF. Finally, the paper compares the performance of a well-tuned MAF-based PLL when using the PI-type LF with the results of using the PID-type LF, which provides useful insights into their capabilities and limitations.

In grid-connected applications, the synchronous reference frame phase-locked loop (SRF-PLL) is a commonly used synchronization technique due to the advantages it offers such as ease of implementation and robust performance. Under ideal grid conditions, the SRF-PLL enables a fast and accurate phase/frequency detection; however, unbalanced and distorted grid conditions highly degrade its performance. To overcome this drawback, several advanced PLLs have been proposed, such as the multiple reference frame-based PLL, the dual second-order generalized integrator-based PLL, and the multiple complex coefficient filter-based PLL. In this paper, a comprehensive design-oriented study of these advanced PLLs is presented. The starting point of this study is to derive the small-signal model of the aforementioned PLLs, which simplifies the parameter design and the stability analysis. Then, a systematic design procedure to fine tune the PLLs parameters is presented. The stability margin, the transient response, and the disturbance rejection capability are the key factors that are considered in the design procedure. Finally, the experimental results are presented to support the theoretical analysis.

Single-phase phase-locked loops (PLLs) are popular for the synchronization and control of single-phase grid-connected converters. They are also widely used for monitoring and diagnostic purposes in the power and energy areas. In recent years, a large number of single-phase PLLs with different structures and properties have been proposed in the literature. The main aim of this paper is to provide a review of these PLLs. To this end, the single-phase PLLs are first classified into two major categories: 1) power-based PLLs and 2) quadrature signal generation-based PLLs. The members of each category are then described and their pros and cons are discussed. This paper provides a deep insight into characteristics of different single-phase PLLs, and therefore, can be considered as a reference for researchers and engineers.

Recently, several advanced phase-locked loop (PLL) techniques have been proposed for single-phase applications. Among these, the Park-PLL and the second-order-generalized-integrator-based PLL are very attractive, owing to their simple digital implementation, low computational burden, and desired performance under frequency-varying and harmonically distorted grid conditions. Despite the wide acceptance and use of these two advanced PLLs, no comprehensive design guidelines to fine-tune their parameters have been reported yet. Through a detailed mathematical analysis, it is shown that these two PLL structures are equivalent to each other, from the control point of view. Then, a linearized model is developed which is valid for both PLLs. The derived model significantly simplifies the stability analysis and the parameter design. To fine-tune the PLL parameters, a systematic design approach is suggested afterward, which guarantees a fast dynamic response, a high disturbance rejection ability, and a robust performance. Finally, the simulation and experimental results are presented to support the theoretical analysis.

To improve the performance of phase-locked loops (PLLs) under adverse grid conditions, incorporating different filtering techniques into their structures have been proposed in the literature. These filtering techniques can be broadly classified into in-loop and preloop filtering techniques depending on their position in the PLL structure. Inspired from the concept of delayed signal cancellation (DSC), the idea of cascaded DSC (CDSC) has recently been introduced as an effective solution to improve the performance of the PLL under adverse grid conditions. However, the focus has been on the application of CDSC operator as the prefiltering stage of PLL, and little work has been conducted on its application as the in-loop filtering stage of PLL. This paper provides a detailed analysis and design of dqCDSC-PLL (PLL with in-loop dq-frame CDSC operator). The study is started with an overview of this PLL. A systematic design method to fine tune its control parameters is then proposed. The performance of the dqCDSC-PLL under different grid scenarios is then evaluated in detail. It is then shown that how using the proportional-integral-derivative controller as the loop filter can improve the response time of dqCDSC-PLL. A detailed comparison between the dqCDSC-PLL and moving average filter (MAF) based PLL (MAF-PLL) is then carried out. Through a detailed mathematical analysis, it is also shown that these PLLs are equivalent under certain conditions. The suggested guidelines in this paper make designing the dqCDSC-PLL a simple and straightforward procedure. Besides, the analysis performed in this paper provides a useful insight for designers about the advantages/disadvantages of dqCDSC-PLL for their specific applications.