This work presents a tri-gate GaN junction high-electron-mobility transistor (JHEMT) concept in which the p–n junction wraps around the AlGaN/GaN fins in the gate region. This tri-gate JHEMT differs from all existing GaN FinFETs and tri-gate HEMTs, as they employ a Schottky or a metal-insulator-semiconductor (MIS) gate stack. A tri-gate GaN JHEMT is fabricated using p-type NiO with the gate metal forming an Ohmic contact to NiO. The device shows minimal hysteresis and a subthreshold slope of 63 ± 2 mV/decade with an on-off current ratio of 10⁸. Compared to the tri-gate MISHEMTs fabricated on the same wafer, the tri-gate JHEMTs exhibit higher threshold voltage (V_TH) and achieve positive V_TH without the need for additional AlGaN recess. In addition, this tri-gate JHEMT with a fin width of 60 nm achieves a breakdown voltage (BV) > 1500 V (defined at the drain current of 1 μA/mm at zero gate bias) and maintains the high BV with the fin length scaled down to 200 nm. In comparison, the tri-gate MISHEMTs with narrower and longer fins show punch-through at high voltages. Moreover, when compared to planar enhancement mode HEMTs, tri-gate JHEMTs show significantly lower channel sheet resistance in the gate region. These results illustrate a stronger channel depletion and electrostatic control in the junction tri-gate compared to the MIS tri-gate and suggest great promise of the tri-gate GaN JHEMTs for both high-voltage power and low-voltage power/digital applications.

We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO₃-xBiFeO₃ (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO₃ (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials.

We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO₃-xBa(Cu_1/3Nb_2/3)O₃ (x = 0.025) (BT-BCN) integrated on to HfO₂ buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO₂ and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current and high and low capacitance values that were easily distinguishable even after ~10⁶ s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology.

In this paper, we benchmark the read/write performance and standby power of several static random access memory (SRAM) cell architectures utilizing 45-nm Si CMOS MOSFET and/or tensile-strained Ge/InGaAs tunnel FET (TFET) devices under low-voltage operation (0.2 V ≤ |V _DD | ≤ 0.6 V). We then introduce a novel tensile-strained Ge/InGaAs TFET-based SRAM circuit using several access schemes and investigate the impact of cell access design on static and dynamic performance. SRAM cells utilizing outward access transistors exhibit wide read and write static noise margins, but suffer from increased read delay times. A 7T SRAM cell architecture is proposed in order to resolve the degraded read delay time. Cell standby energy was found to exhibit a strong dependence on operational voltage and Ge strain state. Variation of the Ge strain state from 1.5% to 3% resulted in an up to 98% reduction in cell standby energy (|V _DD | = 0.6 V) as compared with similar CMOS-based SRAM cells. These results demonstrate the superior performance of the proposed 7T TFET SRAM design for operation in the low- and ultralow-voltage regime.

The structural, morphological, and energy band alignment properties of biaxial tensile-strained germanium epilayers, grown in-situ on GaAs via a linearly graded In _x Ga _1-x As buffer architecture and utilizing dual chamber molecular beam epitaxy, were investigated. Precise control over the growth conditions yielded a tunable in-plane biaxial tensile strain within the Ge thin films that was modulated by the underlying In _x Ga _1-x As “virtual substrate” composition. In-plane tensile strains up to 1.94% were achieved without Ge relaxation for layer thicknesses of 15 to 30 nm. High-resolution x-ray diffraction supported the pseudomorphic nature of the Ge/In _x Ga _1-x As interface, indicating a quasi-ideal stress transfer to the Ge lattice. High-resolution transmission electron microscopy revealed defect-free Ge epitaxy and a sharp, coherent interface at the Ge/In _x Ga _1-x As heterojunction. Surface morphology characterization using atomic force microscopy exhibited symmetric, 2-D cross-hatch patterns with root mean square roughness less than 4.5 nm. X-ray photoelectron spectroscopic analysis revealed a positive, monotonic trend in band offsets for increasing tensile strain. The superior structural and band alignment properties of strain-engineered epitaxial Ge suggest that tensile-strained Ge/In _x Ga _1-x As heterostructures show great potential for future high-performance tunnel field-effect transistor architectures requiring flexible device design criteria while maintaining low power, energy-efficient device operation.

Germanium-based materials and device architectures have recently appeared as exciting material systems for future low-power nanoscale transistors and photonic devices. Heterogeneous integration of germanium (Ge)-based materials on silicon (Si) using large bandgap buffer architectures could enable the monolithic integration of electronics and photonics. In this paper, we report on the heterogeneous integration of device-quality epitaxial Ge on Si using composite AlAs/GaAs large bandgap buffer, grown by molecular beam epitaxy that is suitable for fabricating low-power fin field-effect transistors required for continuing transistor miniaturization. The superior structural quality of the integrated Ge on Si using AlAs/GaAs was demonstrated using high-resolution x-ray diffraction analysis. High-resolution transmission electron microscopy confirmed relaxed Ge with high crystalline quality and a sharp Ge/AlAs heterointerface. X-ray photoelectron spectroscopy demonstrated a large valence band offset at the Ge/AlAs interface, as compared to Ge/GaAs heterostructure, which is a prerequisite for superior carrier confinement. The temperature-dependent electrical transport properties of the n-type Ge layer demonstrated a Hall mobility of 370[emsp14]cm2/Vs at 290[emsp14]K and 457[emsp14]cm2/Vs at 90[emsp14]K, which suggests epitaxial Ge grown on Si using an AlAs/GaAs buffer architecture would be a promising candidate for next-generation high-performance and energy-efficient fin field-effect transistor applications.