We propose a gradient descent type bit flipping algorithm for decoding low density parity check codes on the binary symmetric channel. Randomness introduced in the bit flipping rule makes this class of decoders not only superior to other decoding algorithms of this type, but also robust to logic-gate failures. We report a surprising discovery that for a broad range of gate failure probability our decoders actually benefit from faults in logic gates which serve as an inherent source of randomness and help the decoding algorithm to escape from local minima associated with trapping sets.

Spectrum sharing cognitive radio with transmit antenna selection and maximal ratio combining is analyzed, under the peak interference constraint at the primary user receiver. The ergodic capacity of the secondary link with an arbitrary number of transmit and receive antennas is derived, for the case of Rayleigh fading and transmit power constraint. For the case of unlimited transmit power, the closed-form expression for the capacity is derived. The correctness of analytical results is verified by using an independent simulation model.

In this letter, exact closed form expressions for the level crossing rate and the autocorrelation function are derived for maximum-ratio-combining with independent but unbalanced diversity branches. The novel expressions are given for Rayleigh propagation and an arbitrary number of diversity branches. The derived identities can be applied to isotropic as well as to nonisotropic scattering environment. The analytical results are validated by simulation.

We give an architecture of a storage system consisting of a storage medium made of unreliable memory elements and an error correction circuit made of a combination of noisy and noiseless logic gates that is capable of retaining the stored information with the lower probability of error than a storage system with a correction circuit made completely of noiseless logic gates. Our correction circuit is based on the iterative decoding of low-density parity check codes, and uses the positive effect of errors in logic gates to correct errors in memory elements. In the spirit of Marcus Tullius Cicero's Clavus clavo eicitur (one nail drives out another), the proposed storage system operates on the principle: error errore eicitur-one error drives out another. The randomness that is present in the logic gates makes these classes of decoders superior to their noiseless counterparts. Moreover, random perturbations do not require any additional computational resources as they are inherent to unreliable hardware itself. To utilize the benefits of logic gate failures, our correction circuit relies on two key novelties: a mixture of reliable and unreliable gates and decoder rewinding. We present a method based on absorbing Markov chains for the probability of error analysis, and explain how the randomness in the variable and check node update function helps a decoder to escape to local minima associated with trapping sets.

In this letter, we characterize the effect of data-dependent gate failures on the performance of the Gallager B decoder of low-density parity-check codes. We show that this type of failures makes the decoder dependent on a transmitted codeword, thus rendering inapplicable the traditional analysis tools such as density evolution and trapping sets. By using Monte Carlo simulations, we identify two operating regions: one in which hardware unreliability leads to significant performance degradation and another in which the performance loss is negligible. Based on these results, we propose a simple modification of the decoder that ensures its fault tolerance.