Jong-Seok Kim

Prof. Jong-Seok Kim

orcid

Research Focus & Metrics

Academic Career Length

16Years (2011-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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3 June 2021 in Nature Electronics
Verified
Journal Article
Closed access
PDF file
SCSungwoo Chun
Sungwoo Chun
JKJong-Seok Kim
Jong-Seok Kim
YYYongsang Yoo
Yongsang Yoo
YCYoung In Choi
Young In Choi
SJSung Jun Jung
Sung Jun Jung
Seungjun ParkSeungjun Park
Seungjun Park

26 January 2016 in Sensors
Verified
Journal Article
Open access
PDF file
JKJong-Seok Kim
Jong-Seok Kim
DKDaeyong Kwon
Daeyong Kwon
BCByong-Deok Choi
Byong-Deok Choi
The zero-potential scanning circuit is widely used as read-out circuit for resistive sensor arrays because it removes a well known problem: crosstalk current. The zero-potential scanning circuit can be divided into two groups based on type of row drivers. One type is a row driver using digital buffers. It can be easily implemented because of its simple structure, but we found that it can cause a large read-out error which originates from on-resistance of the digital buffers used in the row driver. The other type is a row driver composed of operational amplifiers. It, very accurately, reads the sensor resistance, but it uses a large number of operational amplifiers to drive rows of the sensor array; therefore, it severely increases the power consumption, cost, and system complexity. To resolve the inaccuracy or high complexity problems founded in those previous circuits, we propose a new row driver which uses only one operational amplifier to drive all rows of a sensor array with high accuracy. The measurement results with the proposed circuit to drive a 4 × 4 resistor array show that the maximum error is only 0.1% which is remarkably reduced from 30.7% of the previous counterpart.

1 August 2021 in Carbon
Verified
Journal Article
Closed access
JKJong-Seok Kim
Jong-Seok Kim
YSYechan So
Yechan So
SLSangmin Lee
Sangmin Lee
CPChanghyun Pang
Changhyun Pang
WPWanjun Park
Wanjun Park
SCSungwoo Chun
Sungwoo Chun

30 November 2021 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
JKJong-Seok Kim
Jong-Seok Kim
JYJin-O Yoon
Jin-O Yoon
BCByong-Deok Choi
Byong-Deok Choi
A very high light-load efficiency low-ripple-voltage pulse-frequency modulation (PFM) buck converter for Internet of Things applications is presented in this article. The PFM buck converter is widely used because of its higher light-load efficiency. However, it has a higher ripple voltage than its pulsewidth modulation counterpart. Although the ripple voltage of a PFM buck converter can be reduced by increasing the output capacitance, we find that this leads to a decrease in the light-load efficiency due to increased controller loss. This problem is analyzed and verified by IC measurements in this article. The proposed PFM buck converter remarkably reduces the controller loss even at low ripple voltages by replacing the static comparator with a dynamic comparator, which provides a high voltage gain, fast evaluation speed, and low power consumption. In addition, to further reduce the controller loss, a dynamic shutdown control method, which selectively turns off control circuits, is used. The proposed PFM buck converter was fabricated with 0.35-μm CMOS technology. The magnitude and variation of the output ripple voltage are 3 and 2 mV, respectively, and the light-load and peak efficiencies are 81.1% and 94.8%, respectively.

17 August 2017 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
JKJong-Seok Kim
Jong-Seok Kim
JJJun-Hwan Jang
Jun-Hwan Jang
YKYong-Duck Kim
Yong-Duck Kim
JBJung-Woo Byun
Jung-Woo Byun
KHKilim Han
Kilim Han
BCByong-Deok Choi
Byong-Deok Choi
Previously reported thin-film transistor (TFT) digital logic gates are mostly static circuits. If the static logic circuits are implemented using either nMOS or pMOS technologies alone, unlike CMOS technologies, the circuits consume high power because of the steady-state current, and take large circuit area. In this paper, the dynamic logic circuits using n-type a-IGZO TFTs are proposed to resolve the power and circuit area issues. The dynamic logic circuits such as inverters and nand gates are fabricated in an amorphous indium-gallium-zinc-oxide TFT technology, and traditional static logic circuits are also implemented with the same technology for comparison purposes. The measurement results show that the proposed dynamic logic circuit consumes no steady-state current, and the circuit area is reduced by 93.1%.

19 June 2018 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
JKJong-Seok Kim
Jong-Seok Kim
JBJung-Woo Byun
Jung-Woo Byun
JJJun-Hwan Jang
Jun-Hwan Jang
YKYong-Duck Kim
Yong-Duck Kim
KHKi-Lim Han
Ki-Lim Han
BCByong-Deok Choi
Byong-Deok Choi
Most thin-film transistor (TFT) gate drivers integrated on the display panel use the carry signals between the stages. In our previous works, we found that these carry-type gate drivers are subject to the reliability problem in a flexible display, since the errors of the stressed stages are accumulated through the carry signals. This problem possibly leads to the failure of image refresh of the display device. Therefore, the carry-free gate driver can resolve the error accumulation problem since it does not use the carry signals and instead, each unit stage operates independently. In this paper, we propose an advanced carry-free gate driver circuit to remove the drawbacks of the previous version, while keeping the advantages. More importantly, this paper is the first report to experimentally show that the error accumulation phenomenon of the carry-type gate driver and the problem is removed in the carry-free gate driver. The proposed carry-free gate driver and the carry-type gate driver are fabricated with amorphous indium-gallium-zinc-oxide TFTs on a flexible substrate for comparison purpose. The proposed gate driver shows a very high reliability since no voltage fluctuation occurs at the outputs after 10 000 cycles bending test with 2-mm bending radius.