This article presents a novel approximate adder that is design-optimized and has optimized error metrics. Optimization in design translates into optimization of the design parameters such as delay, power, and area/resources, and optimization of the error metrics points to the usefulness of the proposed approximate adder for practical applications. We refer to the proposed approximate adder that is hardware optimized and having a near-normal error distribution as HOAANED, in short. We consider the implementation of HOAANED and the other approximate adders based on ASIC and FPGA design environments. We used a Xilinx Artix-7 device for a FPGA implementation, and a 32/28-nm CMOS standard digital cell library for an ASIC based implementation. To demonstrate the practical utility of HOAANED, we considered digital image processing as a practical application and performed experimentation with many images. The quality of the images reconstructed using the approximate adders was analyzed based on the peak signal-to-noise ratio (PSNR), which is used as a qualitative figure-of-merit to assess the images. It is found that HOAANED achieves an improved PSNR in comparison with the other approximate adders for image processing, and this is achieved with HOAANED simultaneously featuring optimized design metrics and error characteristics.

This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.

Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable.

This paper presents a new hardware optimized approximate adder that has practically zero average error and a normal i.e., a Gaussian error distribution. We call the proposed approximate adder HOAANED, which is expanded as hardware optimized approximate adder with a normal error distribution. We considered the use of HOAANED for digital image processing alongside the accurate adder and many other approximate adders for a practical analysis. In particular, the additions involved in performing fast Fourier Transform and inverse fast Fourier transform operations to reconstruct the images were implemented using accurate and approximate adders separately. We found that HOAANED improves the peak signal-to-noise ratio of the reconstructed images better compared to the other approximate adders. Further, HOAANED has optimized design metrics. This observation is based on physical implementation using a 32/28nm CMOS standard digital cell library. Furthermore, based on the error analysis of many 32-bit approximate adders using a million random input vectors we found that HOAANED has practically zero average error, an optimized root mean square error and a normal error distribution.