We demonstrate low subthreshold swing (SS) double-gate (DG) β-Ga2O3 field-effect transistors (FETs) with polycrystalline hafnium oxide (HfO2) gate dielectrics. The atomic layer deposited HfO2 layer at an elevated temperature of 350 0C without post-deposition annealing has a polycrystalline structure. The threshold voltage is modulated from depletion-to enhancement-mode by independently controlled bottom-gate bias. The SS is reduced to as low as 64 mV/dec with mobility of 20 cm2/V7s while maintaining a high on/off ratio of 107 and negligible hysteresis of 30 mV via double-gate operation. The device shows an on/off ratio of 106 and SS of 320 mV/dec up to an operating temperature of 250 0C and off-state breakdown voltage of 355 V. The demonstrated DG β-Ga2O3 FETs with the polycrystalline HfO2 layer is a promising structure for energy efficient high temperature device and circuit applications.
22 April 2019 in IEEE Journal of the Electron Devices Society
We report on the effect of Al 2 O 3 surface passivation on electrical properties of beta-gallium oxide (β-Ga 2 O 3 ) nanomembrane field-effect transistor (FET). The fabricated bottom-gate β -Ga 2 O 3 (100) FET exhibits enhanced channel conductance and reduced hysteresis after the conformal atomic layer deposited Al 2 O 3 passivation investigated by high-resolution transmission electron microscope (HR-TEM) analysis. Moreover, abnormal positive threshold voltage (V TH ) shifts under negative bias stress are turned into negative V TH shifts, and off-state breakdown characteristics is improved as well. A modeling work using physics-based TCAD shows reduced surface depletion effect after the surface passivation. The results demonstrate that high-quality ALD-Al 2 O 3 surface passivation is an effective method to improve electrical properties of the bottom-gate β-Ga 2 O 3 FET and its device applications.
29 January 2021 in IEEE Transactions on Electron Devices
We report the comparison of the atomic layer deposited polycrystalline (p-)/amorphous (a-) HfO 2 bilayer gate dielectric with p-HfO 2 /a-Al 2 O 3 for enhanced β-Ga 2 O 3 metal oxide semiconductor capacitors (MOSCAPs). A discrepancy in the temperature-dependent hysteretic behaviors is observed, and thus, pulse capacitance- voltage (C-V) measurements are employed to investigate interface properties at the border between the amorphous (Al 2 O 3 or HfO 2 ) and polycrystalline (HfO 2 ) oxide layers. The proposed p-HfO 2 /a-HfO 2 exhibits similar interface trap densities (Dit) at the interface between the bilayer dielectric and β-Ga 2 O 3 , and shows lower border trap density (Nbt). An effective barrier height of 1.62 eV for the p-HfO 2 /a-HfO 2 with a breakdown field of 9.1 MV/cm, which is higher than 1.01 eV of p-HfO 2 /a-Al 2 O 3 , is obtained from the current density-voltage (J-V) characteristics using the Folwer-Nordheim model. Moreover, as compared with a p-HfO 2 single layer, the additional a-HfO 2 layer on top of p-HfO 2 is beneficial to improve hysteretic and leakage characteristics, while maintaining its high-quality interface. The p-HfO 2 /a-HfO 2 bilayer with improved interface properties as well as a large positive flat-band voltage of 4.7 V is a promising candidate for the metal/high-k-stack of β-Ga 2 O 3 MOSCAPs.
Interface traps between a gate insulator and beta-gallium oxide (β-Ga2O3) channel are extensively studied because of the interface trap charge-induced instability and hysteresis. In this work, their effects on mobility degradation at low temperature and hysteresis at high temperature are investigated by characterizing electrical properties of the device in a temperature range of 20–300 K. As acceptor-like traps at the interface are frozen below 230 K, the hysteresis becomes negligible but simultaneously the channel mobility significantly degrades because the inactive neutral traps allow additional collisions of electrons at the interface. This is confirmed by the fact that a gate bias adversely affects the channel mobility. An activation energy of such traps is estimated as 170 meV. The activated trap charges’ trapping and de-trapping processes in response to the gate pulse bias reveal that the time constants for the slow and fast processes decrease due to additionally activated traps as the temperature increases.