Imbalanced voltage sharing during the turn-off transient is a challenge for series-connected silicon carbide (SiC) MOSFET application. This article first discusses the influence of the gate-drain discharge deviation on the voltage imbalance ratio, and its primary causes are also presented and verified by LTspice simulation. Accordingly, a novel active gate drive, which aims to compensate the discharge difference between devices connected in series, is proposed and analyzed. By only using the original output of the driving IC, the proposed gate drive is realized by implementing an auxiliary circuit on the existing commercial gate drive. Therefore, unlike other active gate drives for balancing control, no extra isolations for power/signal are needed, and the number of the devices in series is unlimited. The auxiliary circuit includes three subcircuits as a high-bandwidth current sink for regulating switching performance, a relative low-frequency but reliable sampling and control circuit for closed-loop control, and a trigger combining the former and the latter. The operational principle and the design guideline for each part are presented in detail. Experimental results validate the performance of the proposed gate drive and its voltage balancing control algorithm.

Active gate drive with high accurate and self-adaptive closed-loop control is a promising approach to solving the imbalanced voltage problem of series-connected silicon carbide (SiC) mosfet s. However, due to the inherent time propagation mismatching between Si- and SiC-based devices, behavior adjustment through Si-based ICs during the switching transient takes at least tens of nanoseconds, which limits the minimum allowable turn- off time of each series unit. In this article, a novel active gate drive with a variable gate voltage regulator (GVR) is proposed. It uses a single P-channel mosfet to determine the connection timing of a precharged capacitor in series with the input capacitance in which way the switching transient of each device in the stack is adjustable. It is more advantageous when applied to the low-power SiC mosfet applications with relatively smaller external gate resistors. Two sampling and voltage balancing control circuits based on different processors are proposed for the GVR to adapt to different switching frequencies and costs. Its operational principle and design guidelines are specified and its performance on voltage balancing control is experimentally verified. Analytical assessment on switching losses and costs, compared with the previous work, is provided.

Inverters generate significant EMI due to their rapid switching operations. This paper proposes an EMI suppression scheme at the source level based on a series IGBT topology and voltage shaping. By reshaping the output voltage waveform, the scheme periodically suppresses the EMI source. Furthermore, staircase voltage shaping is implemented using a CPLD-based sequential gate drive circuit, eliminating the need for complex modifications to existing gate drive circuits. Experimental results on an 1140 V explosion-proof induction motor drive platform demonstrate that this method achieves harmonic attenuation of 4-20 dBμV within a 2 MHz bandwidth period. Compared to traditional two-level inverters, total switching losses are reduced by around 70%. Periodic EMI suppression also simplifies the design complexity of other EMI mitigation methods within the system. Its periodic nature also enhances design predictability. Moreover, this approach leverages the flexibility and scalability of the series IGBT structure to provide a practical solution for high-voltage inverter systems. It enables source-level EMI suppression without significantly increasing system complexity or cost.

Stacking SiC mosfets in series is an effective approach to enhance voltage rating and simplify topologies of high-power converters. Beyond the dynamic voltage balancing during normal switching operations, short-circuit (SC) detection and protection are equally critical. Discrepancies in gate drive timing and inherent mismatches in the I–V characteristics among series-connected devices not only complicate SC detection but also induce imbalanced voltage sharing with elevated current, posing a significant challenge for conventional SC detection circuits and snubbers. To solve these issues, a novel SC detector (SCD) and soft turn-off (STO) circuit designed for series-connected SiC mosfets are proposed in this article. Based on the voltage slope of the entire power stack, the SCD is compatible with both hard switching fault and fault under load (FUL) conditions. The STO circuit can be directly integrated into conventional concentrated clamping snubber. It can actively limit the current through each series-stacked SiC mosfet during an SC event, while balancing the fault energy distribution among devices and mitigating the risk of excessive power dissipation. The design guidelines as well as detailed selection principles for the components of each sub-circuit are specified. Furthermore, the performance of the proposed SC detection and protection scheme is experimentally verified based on the established test platform.