Satish G. Kandlikar

Satish G. Kandlikar


Research Focus & Metrics

Academic Career Length

26Years (2001-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 January 2005 in Journal of Heat Transfer
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Journal Article
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ABA. E. Bergles
A. E. Bergles
SKSatish G. Kandlikar
Satish G. Kandlikar

26 July 2013 in Journal of Heat Transfer
Verified
Journal Article
Closed access
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SKSatish G. Kandlikar
Satish G. Kandlikar
Stéphane ColinStéphane Colin
Stéphane Colin
YPYoav Peles
Yoav Peles
Srinivas GarimellaSrinivas Garimella
Srinivas Garimella
RPR. Fabian Pease
R. Fabian Pease
DTDavid B. Tuckerman
David B. Tuckerman

2 December 2005 in Journal of Heat Transfer
Verified
Journal Article
Closed access
PDF file
SKSatish G. Kandlikar
Satish G. Kandlikar
WKWai Keat Kuan
Wai Keat Kuan
DWDaniel A. Willistein
Daniel A. Willistein
JBJohn Borrelli
John Borrelli

29 April 2014 in Journal of Electronic Packaging
Verified
Journal Article
Closed access
PDF file
SKSatish G. Kandlikar
Satish G. Kandlikar
In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50–100 W/cm2 on each side of a chip in a 3D IC package, the current single-phase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500 W/cm2, significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200 μm or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops.