In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the discrete cosine transform/discrete sine transform/inverse discrete cosine transform/inverse discrete sine transform based on an appropriate formulation of the four transforms into cyclic convolution structures is presented. This formulation allows an efficient memory-based systolic array implementation of the unified architecture using dual-port ROMs and appropriate hardware sharing methods. The performance of the unified design is compared to that of some of the existing ones. It is found that the proposed design provides a superior performance in terms of the hardware complexity, speed, I/O costs, in addition to such features as regularity, modularity, pipelining capability, and local connectivity, which make the unified structure well suited for VLSI implementation.

A new very large scale integration (VLSI) algorithm for a 2N-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the subexpression sharing technique that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI.

Using a specific input-restructuring sequence, a new VLSI algorithm and architecture have been derived for a high throughput memory-based systolic array VLSI implementation of a discrete cosine transform. The proposed restructuring technique transforms the DCT algorithm into a cycle-convolution and a pseudo-cycle convolution structure as basic computational forms. The proposed solution has been specially designed to have good fixed-point error performances that have been exploited to further reduce the hardware complexity and power consumption. It leads to a ROM based VLSI kernel with good quantization properties. A parallel VLSI algorithm and architecture with a good fixed point implementation appropriate for a memory-based implementation have been obtained. The proposed algorithm can be mapped onto two linear systolic arrays with similar length and form. They can be further efficiently merged into a single array using an appropriate hardware sharing technique. A highly efficient VLSI chip can be thus obtained with appealing features as good architectural topology, processing speed, hardware complexity and I/O costs. Moreover, the proposed solution substantially reduces the hardware overhead involved by the pre-processing stage that for short length DCT consumes an important percentage of the chip area.

In this paper, we present a new systolic algorithm for an efficient design approach using a bi-port memory-based VLSI implementation of the DHT. Using auxiliary input and output sequences and appropriate permutations it is shown that it is possible to compute a prime-length DHT using two cyclic convolutions having the same form and length that can be computed in parallel leading to improve throughput with a reduced hardware and I/O costs. The two computation structures can be mapped on the same linear systolic array using an appropriate hardware-sharing technique. Adopting a bi-port memory-based systolic architecture we can further reduce the hardware complexity and I/O costs while preserving all the advantages of a cyclic convolution based systolic array implementation such as regularity, modularity and a good topology of the interconnection structure.

In this paper, a unified design framework for prime-length forward and inverse discrete cosine transforms with a high throughput is presented. The proposed design facilitates trade-off between the throughput and hardware cost or power consumption, and is well suited for low-power applications. The VLSI structure is highly regular and modular with a topology well suited for the VLSI implementation. The proposed approach is based on the derivation of new efficient systolic algorithms. The algorithms have the same core structure for both the transforms, and the core structure consists of two circular correlations, which unlike other similar computational structures, have the same length and form. Thus, they can be computed in parallel and mapped on the same linear systolic array with channels having a low I/O bandwidth requirement and their number being independent of the transform length N. Further, it is shown that the two transforms, can be efficiently implemented on the same VLSI chip, where only the pre- and post-processing stages are different. The proposed systolic algorithms retain the benefits provided by VLSI implementations based on circular or cyclic convolution structures, and at the same time has a simpler control structure, high speed and low complexity

In this brief, a new efficient radix-2 fast algorithm for the computation of type-III discrete Hartley transform of length that has a small arithmetic cost and is well suited for a very large-scale integration (VLSI) implementation is presented. This recursive method requires a small number of arithmetic operations compared with existing methods, has a regular and simple computational structure, and can be easily implemented. A small number of arithmetic operations are achieved with the proposed algorithm as compared with existing algorithms. Moreover, the regular and simple computational structure and the existing parallelism of the proposed algorithm offer the possibility of an efficient fast parallel VLSI implementation.