Off-the-shelf embedded systems have adopted heterogeneous multi-core processors which have high-performance big cores and low-power small cores. Though there are two different types of cores in heterogeneous multi-core processors, conventional DVFS (Dynamic Voltage and Frequency Scaling)-based DTM (Dynamic Thermal Management) techniques do not utilize the different types of cores to cool down hot cores. Rather, they primarily reduce the voltage and frequency of the hot cores, leading to performance degradation. In this paper, we propose a novel adaptive DTM framework for heterogeneous multi-core processors, which utilizes the big and small cores to prevent performance degradation. Our proposed framework exploits two migration-based DTM techniques: 1) a technique (denoted as $\text{Migration}_{\text{big}\longleftrightarrow \text{big}}$ }) that migrates applications from hot big cores (big cores whose temperature is above a pre-defined threshold) to cold big cores (big cores whose temperature is below the threshold) and 2) a technique (denoted as $\text{Migration}_{\text{big}\longleftrightarrow \text{small}}$ ) that migrates all applications from the big cores to the small cores. In case of thermal emergency of the big cores, our proposed framework checks the number of cold big cores. When there exist available cold big cores, our proposed framework employs $\text{Migration}_{\text{big}\longleftrightarrow \text{big}}$ to cool down the hot big cores while not reducing the big core frequency. On the other hand, when there does not exist any available cold big core, our proposed framework employs one between $\text{Migration}_{\text{big}\longleftrightarrow \text{small}}$ and a DVFS-based DTM technique, which is expected to result in better performance. In our experiments on an embedded development board, our proposed framework improves the average performance by 8.9%, compared to ARM's DVFS-based IPA (Intelligent Power Allocation), satisfying thermal constraints. Our framework also improves the average performance by 10.4%, compared to a state-of-the-art predictive DVFS-based DTM technique.

To improve mobile experience of users, recent mobile devices have adopted powerful processing units (CPUs and GPUs). Unfortunately, the processing units often consume a considerable amount of energy, which in turn shortens battery life of mobile devices. For energy reduction of the processing units, mobile devices adopt energy management techniques based on software, especially OS (Operating Systems), as well as hardware. In this survey paper, we summarize recent OS-level energy management techniques for mobile processing units. We categorize the energy management techniques into three parts, according to main operations of the summarized techniques: 1) techniques adjusting power states of processing units, 2) techniques exploiting other computing resources, and 3) techniques considering interactions between displays and processing units. We believe this comprehensive survey paper will be a useful guideline for understanding recent OS-level energy management techniques and developing more advanced OS-level techniques for energy-efficient mobile processing units.

Thermal issues are plaguing high-performance systems because of their high power consumption, and mobile systems because of their form factor and compactness. Researchers have developed tools and design methodologies to model, predict, and optimize thermal aspects, but it has remained a challenge to validate them against real systems. This paper is valuable by focusing on a commercial mobile application processor and validating the widely used models in the research community with experimental measurements using an IR camera.

On-demand cooling is inevitable to maximize the processor's performance, while fulfilling thermal constraints - this holds more in advanced technologies, where localized hot spots changes during run-time. In this work, we propose to adopt an array of thin-film thermoelectric (TE) devices, that is integrated within the chip packaging, for both cooling and energy-harvesting purposes. Each TE device within the array can be during run-time enabled either for energy harvesting or on-demand cooling. Our approach is implemented and evaluated using mature Finite Elements Analysis tool in which a commercial multi-core mobile chip is modeled after careful calibrations together with state-of-the-art TE devices. Results demonstrate that our approach reduces the peak temperature by up to 24 °C and the average temperature by 10 °C across various benchmarks with the cost of 67.5 mW. Additionally, the harvested energy from the array of TE devices compensates for 89 % of the required cooling energy