A novel True Random Number Generator circuit fabricated in a 130 nm HfO ₂ -based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, all the cells of the memory array are addressed at the same time while the current provided to the circuit is limited to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, other cells are slightly programmed to reach an intermediate resistance state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed twelve NIST tests out of fifteen. Compared to state-of-the-art resistive RAM-based true random number generators, our proposed methodology is the first one to leverage on programming current limitation at a memory array level.

In this paper a new experimental technique for measuring the switching dynamics and extracting the energy consumption of Spin Transfer Torque MRAM (STT-MRAM) device is presented. This technique is performed by a real-time current reading while a pulsed bias is applied. The switching from a high resistive state, anti-parallel (AP) alignment, to a low resistive state, parallel (P) alignment, is investigated as well as the impact of the cell diameter on the switching parameters. We demonstrate that preswitching and switching times and energies have a log-linear relationship with the applied voltage. Increasing the applied voltage leads to a higher spin torque on the free layer in a shorter time. This decreases the time needed to change the magnetization orientation of this layer, thus the time required before the switching occurs. We have also shown that for a given applied voltage, the smaller the cell the longer the time before switching. For low applied voltages, the preswitching time increases exponentially dominating the whole reversal time. The longer switching times can be explained by a lower Joule heating not sufficient to induce the thermally activated reversal process. This phenomenon is accentuated for smaller cells, where the heating is more significant and the time before switching is shorter than for larger cells.

Characterizing and quantifying the endurance of Resistive RAM devices is critical to assess their reliability for integration in electronic systems. This paper proposes a novel characterization methodology for rapid detection of RRAMs reliability issues during endurance tests. A test structure consisting of an array of non-addressable RRAM memory cells with parallel connection of all the memory elements is used for this purpose. The test structure fills the gap between isolated cells and circuit level endurance tests as it combines the test speed of an isolated cell while providing at the same time data from multiple devices. Endurance tests are conducted while monitoring RRAM electrical parameters of interest for each switching cycle. Experimental results show that most studies that claimed high endurance without capturing all switching cycles, or by considering an isolated cell, lead to an overestimation of the endurance. Finally, an endurance failures mitigation scheme based on RRAM current sensing in the RESET direction is presented to improve the endurance.

Conductive Bridge Random Access Memories (CBRAMs) are promising candidates for memory applications on flexible substrates. In this study, mesoporous SiO ₂ CBRAM memory cells were fabricated and tested using a low-temperature process as low as 120°C, making them compatible with various flexible substrates. A comparative study was conducted to validate the characteristics and performance of these memory cells in relation to conventional manufacturing process. We demonstrate the non-volatile characteristics of the cells, which feature low switching voltages, a high resistance ratio of 10 ⁴ between high and low resistance states, and reliable bipolar switching behavior, enduring over 10 ³ write-read-erase-read cycles. Furthermore, memory cells fabricated on PET substrates using the low-temperature process show stable and highly promising responses to mechanical stress. These results pave the way for the fabrication of simple, low-cost crossbar memory arrays on flexible substrates using a combination of sol-gel and inkjet-printing processes.

One of the important features of Resistive RAM (RRAM) is its conductance modulation, which makes it suitable for neuromorphic computing systems. In this paper, the conductance modulation of Oxide-based RAM (OxRAM) devices is evaluated based on experimental data to reveal its inherent analog synaptic behavior. A test chip made of a classical 1T-1R elementary memory array is used to demonstrate the conductance modulation. Using an array of cells, as opposed to an isolated cell, allows to catch temporal as well as spatial variabilities. Thus, the multiple resistance levels capability of OxRAMs is assessed in a more realistic context. Two different programming techniques are used to program the OxRAM cells. The first approach leverages on RESET (RST) voltage control. The second approach relies on compliance current control during the SET operation. In both approaches, although multiple resistance levels can be easily obtained, it is demonstrated that a successful implementation of a reliable conductance modulation scheme mainly depends on the ability to precisely control the impact of variability on the different conductance levels obtained after the programming operation.