A single event transient (SET) due to alpha particle strike is studied in 11 and 6 nm bulk FinFETs and 6 nm bulk nanosheet FET using three dimensional TCAD Simulation. The nanosheet device shows superior immunity to alpha particles due to the strong gate controllability. The floating nanosheets isolated from the bulk substrate and the surrounding gate structure suppress charging due to ionization radiation. The angular irradiation effect is also studied. The impact of the incident angle is less sensitive in the nanosheet FET compared to the FinFET. This is attributed to the fact that the channel is segmented into three stacks with each controlled by the surrounding gate, thereby physically decoupling the transient charges and reducing the SET in the nanosheet FET.

A new dynamic random access memory (DRAM) memory cell transistor is fabricated, and its soft-error immunity and rowhammer tolerance are studied. The vertical channel is formed by selective epitaxial growth of silicon pillar, and the surround gate forms a fully depleted (FD) channel, which can suppress floating-body effects, such as hysteresis. A TCAD simulation study compares this device and conventional bulk saddle FinFET in terms of soft error immunity and rowhammer tolerance. The confined channel limits soft error because of its thin channel volume for charge generation due to alpha and neutron particles. The surround gate device is inherently free from rowhammer attack as each silicon body of any memory cell transistor is fully isolated from neighboring word lines.

As Fin Field Effect Transistor (FinFET) scales aggressively, even a single point defect becomes a source of performance variability. The point defect is inevitably introduced not only by process damage such as epitaxial growth and ion implantation but also by cosmic rays. Technology computer-aided design (TCAD) is able to simulate the characteristics of the device with the defect. In this work, a machine learning algorithm is tested if it can reproduce the TCAD results. The impact of point defect in bulk FinFET is used as test vehicle to validate the machine-learning algorithm. TCAD is used first to generate a massive number of current-voltage characteristics dataset. The TCAD dataset is then exclusively divided into groups for machine learning training, validation and test. The trained model provides high accuracy test results within 1 % error, showing the possibility to expedite failure analysis cycle via machine learning.

The variability due to the displacement damage defect is investigated for various bulk FinFET technology nodes. A random displacement damage from point to clustered defects is introduced by natural terrestrial radiation in arbitrary locations in the silicon channel region. Energy level, position, and size of the defect clusters are considered as variables, and the impact on device performance is investigated for various technology nodes with the aid of the TCAD simulation. It is found that even a displacement defect can cause significant device degradation as the technology node scales down beyond the 10-nm node. Particularly, the abnormal variability may become an issue at sub-6-nm node due to a limited volume of the fin width and the comparable size of the cluster defect.

Minimizing the variation in threshold voltage (V_t) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize V_t variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., L_g: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.

Soft error effects due to the alpha particle and terrestrial neutron strike are investigated in a saddle fin DRAM using the 3D TCAD simulation. The strike location and angle dependency are investigated, and the worst-case incidence condition is studied. As the strike time is relevant for the error pattern, the strike during the write period is found to have minor effect, but the strike during the hold period shows data corruption. The inter-active disturbance is effectively suppressed due to the shallow trench isolation, but the inter-active ionizing radiation disturbance can be a potential risk as the capacitance of the storage capacitor continues to reduce with the DRAM technology scaling.