In the context of growing the adoption of advanced sensors and systems for active vehicle safety and driver assistance, an increasingly important issue is the security of the information exchanged between the different sub-systems of the vehicle. Random number generation is crucial in modern encryption and security applications as it is a critical task from the point of view of the robustness of the security chain. Random numbers are in fact used to generate the encryption keys to be used for ciphers. Consequently, any weakness in the key generation process can potentially leak information that can be used to breach even the strongest cipher. This paper presents the architecture of a high performance Random Number Generator (RNG) IP-core, in particular a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications. The specifications used to develop the proposed project were derived from dedicated literature and standards. Subsequently, specific architecture optimizations were studied to achieve better timing performance and very high throughput values. The IP-core has been validated thanks to the official NIST Statistical Test Suite, in order to evaluate the degree of randomness of the numbers generated in output. Finally the CSPRNG IP-core has been characterized on relevant Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies.

In recent years there have been significant developments in satellite transmitter technology to follow the rapid innovation of sensors on-board new satellites. The CCSDS 131.2-B-1 standard for telemetry downlink, released in 2012, is part of the next generation of standards that aims to support the increased data-rate caused by these improvements in resolution. As a result of its relative novelty, this standard currently lacks in-depth analysis by researchers, but it is also strongly supported by the European Space Agency (ESA) for future missions. For these reasons, it seems important to evaluate how major receiver sub-components, such as timing recovery and carrier frequency correction, can be designed and implemented in new receivers that support this standard. The timing error detectors (TED) and frequency error detectors (FED) were therefore studied on the specific peculiarities of CCSDS 131.2-B-1 in its usual environment of Low Earth Orbit (LEO). Estimators have been evaluated highlighting performances, trade-offs and peculiarities of each one with respect to corresponding architectural choices. Finally, a receiver architecture derived from the paper considerations is proposed in the aim of supporting very different mission scenarios. Specifically, the realized architecture employs a parallel feedforward estimator for the timing recovery section and a novel multi-algorithm feedback frequency correction loop to efficiently cover both low symbol rates (5 Mbaud) and high data-rates (up to 500 Mbaud). This solution represents a good trade-off to support these scenarios in a very compact footprint by pushing the clock frequency to the FPGA limit. The FPGA resources occupation on a Zynq Ultrascale+ RFSoC XCZU28DR FPGA is 5202 LUT, 4851 FF, 5 BRAM, and 21 DSP for the timing recovery part, while the frequency recovery section occupies 1723 LUT, 1511 FF, 2.5 BRAM and 32 DSP.

To ensure the flexibility of Earth Observation satellite missions, it is essential to have highly adaptable communication systems equipped with efficient modulation and coding schemes. The preferred approach for such applications is the DVB-S2 standard, which provides three operational modes: Constant Coding and Modulation, Variable Coding and Modulation, and Adaptive Coding and Modulation. Additionally, this standard incorporates a robust Forward Error Correction system that combines a Low-Density Parity-Check encoder with a Bose-Chaudhuri-Hocquenghem encoder. This combination ensures optimal utilization of channel bandwidth while maintaining an acceptable Bit Error Rate throughout the satellite’s orbit. This research is centred on designing and implementing a highly flexible and high-speed parallel Bose-Chaudhuri-Hocquenghem encoder, fully compliant with the DVB-S2 standard, and supporting all Constant Coding and Modulation, Variable Coding and Modulation, and Adaptive Coding and Modulation modes. In contrast to existing solutions, our proposed encoder permits the concurrent processing of a larger number of bits, thereby enhancing parallelism. Furthermore, parallelism is a configurable parameter, allowing seamless system scalability. The proposed encoder can be tailored to accommodate a wide range of throughput requirements, making it suitable for various mission classes. This flexibility enables users to balance factors like complexity, power consumption, and performance. The hardware platform selected for circuit implementation is the space-grade Xilinx XQRKU060 FPGA. Our results demonstrate a maximum achievable throughput ranging from 600 Mbps to 19.2 Gbps and a dynamic power consumption of 10 mW to 79 mW, depending on the chosen parallelism level (ranging from 2 to 96). The optimization of resource utilization is particularly noteworthy, as it reduces the required resources to as low as 760 Look-up Tables and 344 registers for lower parallelism levels.

The continuous technical advancement of scientific space missions has resulted in a surge in the amount of data that is transferred to ground stations within short satellite visibility windows, which has consequently led to higher throughput requirements for the hardware involved. To aid synchronization algorithms, the communication standards commonly used in such applications define a physical layer frame structure that is composed of a preamble, segments of modulation symbols, and segments of pilot symbols. Therefore, the detection of a frame start becomes an essential operation, whose accuracy is undermined by the large Doppler shift and quantization errors in hardware implementations. In this work, we present a design methodology for frame synchronization modules that are robust against large frequency offsets and rely on a parallel architecture to support high throughput requirements. Several algorithms are evaluated in terms of the trade-off between accuracy and resource utilization, and the best solution is exemplified through its application to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards. The implementation results are reported for a Xilinx KU115 FPGA, thereby showing the capability of supporting baud rates that are greater than 2 Gbaud, as well as a corresponding throughput of 15.80 Gbps. To the best of our knowledge, this paper is the first to propose a design methodology for parallel frame synchronization modules that has applicability to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards.