This paper studies the reliability of three different majority gates full adder (FA) designs, and compares them with that of a standard XOR-based FA. The analysis provides insights into different parameters that affect the reliability of FAs. The probability transfer matrix method is used to exactly calculate the reliability of the FAs under investigation. All simulation results show that majority gates FAs are more robust than a standard XOR-based FA. They also show how different gates affect the FAs' reliabilities and are extrapolated to give reliability estimates from the device level. Such reliability analyses should be used for a better characterization of FA designs for future nanoelectronic technologies, in addition to the well-known speed and power consumption (which have long been used for selecting and ranking FA designs).

Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the functionality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges associated with scaling is the expected increase of static and dynamic parameter fluctuations and variations, as well as intrinsic and extrinsic noises, with significant effects on reliability. Therefore, there is a clear, growing need for electronic design automation (EDA) tools that can predict the reliability of future massive nano-scaled designs with very high accuracy. Such tools are essential to help VLSI designers optimize the conflicting tradeoffs between area-power-delay and reliability requirements. In this paper, we introduce an EDA tool that quickly and accurately estimates the reliability of any CMOS gate. The tool improves the accuracy of the reliability calculation at the gate level by taking into consideration the gate's topology, the reliability of the individual devices, the applied input vector, as well as the noise margins. It can also be used to estimate the effect on different types of faults and defects, and to estimate the effects of enhancing the reliability of individual devices on the gate's overall reliability.

In this paper we study small hammock networks, more precisely the 29 hammock networks presented by Moore and Shannon in their prescient paper from 1956, where this type of network was introduced. We will first of all review the concept of the reliability polynomial, and define hammock networks, emphasizing some of their properties. We will then review the state-of-the-art from three different angles: theoretical, algorithmic, and design oriented. These will show that results obtained over many years advocate very strongly for small hammock networks. Because array-based designs (e.g., FinFETs) seem to be a perfect fit for small hammocks (as are nanoelectromecanical systems, or NEMS), we have decided to start investigating them closely. The analyses we pursue here are exact, the coefficients of the reliability polynomials being determined using our own program. The reliability polynomials for nontrivial hammock networks are reported here as functions of the probability (p) that the device is closed. As far as we know, this is the first time they have appeared in this form. Our purpose in determining exact results is a practical one, as we foresee that small hammock networks could play a key role in any arraybased design. That is why their reliability enhancements are evaluated thoroughly, using both classical and non-standard cost functions. Finally, conclusions are followed by a longer list of future directions of research, some of them practical while others more theoretical.